Search

Ji H. Bae

Examiner (ID: 18876, Phone: (571)272-7181 , Office: P/2115 )

Most Active Art Unit
2115
Art Unit(s)
2187, 2115, 2118, 2176
Total Applications
984
Issued Applications
775
Pending Applications
53
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9431140 [patent_doc_number] => 08707227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'Method and apparatus for synthesis of multimode x-tolerant compressor' [patent_app_type] => utility [patent_app_number] => 13/304134 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6040 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13304134 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/304134
Method and apparatus for synthesis of multimode x-tolerant compressor Nov 22, 2011 Issued
Array ( [id] => 8831870 [patent_doc_number] => 20130132915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'NETWORK FLOW BASED DATAPATH BIT SLICING' [patent_app_type] => utility [patent_app_number] => 13/301107 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13301107 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/301107
Network flow based datapath bit slicing Nov 20, 2011 Issued
Array ( [id] => 8214306 [patent_doc_number] => 20120131533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'METHOD OF FABRICATING AN INTEGRATED CIRCUIT PROTECTED AGAINST REVERSE ENGINEERING' [patent_app_type] => utility [patent_app_number] => 13/299267 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7758 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131533.pdf [firstpage_image] =>[orig_patent_app_number] => 13299267 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/299267
Method of fabricating an integrated circuit protected against reverse engineering Nov 16, 2011 Issued
Array ( [id] => 9532651 [patent_doc_number] => 08756537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Methods for making contact device for making connection to an electronic circuit device and methods using the same' [patent_app_type] => utility [patent_app_number] => 13/373235 [patent_app_country] => US [patent_app_date] => 2011-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 42 [patent_no_of_words] => 18118 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13373235 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/373235
Methods for making contact device for making connection to an electronic circuit device and methods using the same Nov 6, 2011 Issued
Array ( [id] => 8334260 [patent_doc_number] => 20120200963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'SYSTEM AND METHOD FOR PROTECTING A COMPUTING DEVICE USING VSD MATERIAL, AND METHOD FOR DESIGNING SAME' [patent_app_type] => utility [patent_app_number] => 13/291090 [patent_app_country] => US [patent_app_date] => 2011-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13291090 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291090
SYSTEM AND METHOD FOR PROTECTING A COMPUTING DEVICE USING VSD MATERIAL, AND METHOD FOR DESIGNING SAME Nov 6, 2011 Abandoned
Array ( [id] => 10890741 [patent_doc_number] => 08914756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Process for fabricating an integrated circuit comprising an analog block and a digital block, and corresponding integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/287347 [patent_app_country] => US [patent_app_date] => 2011-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3293 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287347 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/287347
Process for fabricating an integrated circuit comprising an analog block and a digital block, and corresponding integrated circuit Nov 1, 2011 Issued
Array ( [id] => 8558297 [patent_doc_number] => 08332784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/285650 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 4611 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285650 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285650
Semiconductor device Oct 30, 2011 Issued
Array ( [id] => 8504733 [patent_doc_number] => 20120304141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'Power Mesh for Multiple Frequency Operation of Semiconductor Products' [patent_app_type] => utility [patent_app_number] => 13/253489 [patent_app_country] => US [patent_app_date] => 2011-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8121 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13253489 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/253489
Power mesh for multiple frequency operation of semiconductor products Oct 4, 2011 Issued
Array ( [id] => 8752269 [patent_doc_number] => 08418113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-09 [patent_title] => 'Consideration of local routing and pin access during VLSI global routing' [patent_app_type] => utility [patent_app_number] => 13/252067 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4758 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13252067 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/252067
Consideration of local routing and pin access during VLSI global routing Oct 2, 2011 Issued
Array ( [id] => 8979121 [patent_doc_number] => 20130212551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'POWER SUPPLY CIRCUIT DESIGN SYSTEM AND POWER SUPPLY CIRCUIT DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 13/879284 [patent_app_country] => US [patent_app_date] => 2011-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 19442 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13879284 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/879284
Power supply circuit design system and power supply circuit design method Sep 25, 2011 Issued
Array ( [id] => 8699183 [patent_doc_number] => 20130061192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-07 [patent_title] => 'Re-Modeling a Memory Array for Accurate Timing Analysis' [patent_app_type] => utility [patent_app_number] => 13/227017 [patent_app_country] => US [patent_app_date] => 2011-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7170 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13227017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/227017
Re-modeling a memory array for accurate timing analysis Sep 6, 2011 Issued
Array ( [id] => 10099060 [patent_doc_number] => 09135373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-15 [patent_title] => 'Method and system for implementing an interface for I/O rings' [patent_app_type] => utility [patent_app_number] => 13/219517 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 13224 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219517 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219517
Method and system for implementing an interface for I/O rings Aug 25, 2011 Issued
Array ( [id] => 7770039 [patent_doc_number] => 20120036171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'METHOD AND SYSTEM OF CONVERTING TIMING REPORTS INTO TIMING WAVEFORMS' [patent_app_type] => utility [patent_app_number] => 13/206126 [patent_app_country] => US [patent_app_date] => 2011-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9221 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20120036171.pdf [firstpage_image] =>[orig_patent_app_number] => 13206126 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/206126
Method and system of converting timing reports into timing waveforms Aug 8, 2011 Issued
Array ( [id] => 8716271 [patent_doc_number] => 08402424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Support apparatus, control method, and control program' [patent_app_type] => utility [patent_app_number] => 13/185107 [patent_app_country] => US [patent_app_date] => 2011-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10361 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13185107 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/185107
Support apparatus, control method, and control program Jul 17, 2011 Issued
Array ( [id] => 8608756 [patent_doc_number] => 20130014068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'COMPUTER-AIDED DESIGN SYSTEM AND METHODS THEREOF FOR MERGING DESIGN CONSTRAINT FILES ACROSS OPERATIONAL MODES' [patent_app_type] => utility [patent_app_number] => 13/178607 [patent_app_country] => US [patent_app_date] => 2011-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4212 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178607 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/178607
Computer-aided design system and methods thereof for merging design constraint files across operational modes Jul 7, 2011 Issued
Array ( [id] => 8946079 [patent_doc_number] => 08499266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Race logic synthesis for large-scale integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 13/167237 [patent_app_country] => US [patent_app_date] => 2011-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 40 [patent_no_of_words] => 11689 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167237 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167237
Race logic synthesis for large-scale integrated circuit designs Jun 22, 2011 Issued
Array ( [id] => 9348290 [patent_doc_number] => 08667453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Power-supply design system, power-supply design method, and program for power-supply design' [patent_app_type] => utility [patent_app_number] => 13/811886 [patent_app_country] => US [patent_app_date] => 2011-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13811886 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/811886
Power-supply design system, power-supply design method, and program for power-supply design Jun 19, 2011 Issued
Array ( [id] => 9116350 [patent_doc_number] => 08572542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Clock-tree structure and method for synthesizing the same' [patent_app_type] => utility [patent_app_number] => 13/160847 [patent_app_country] => US [patent_app_date] => 2011-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 6345 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13160847 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/160847
Clock-tree structure and method for synthesizing the same Jun 14, 2011 Issued
Array ( [id] => 10182132 [patent_doc_number] => 09211800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-15 [patent_title] => 'Battery system and control method of battery system' [patent_app_type] => utility [patent_app_number] => 13/581298 [patent_app_country] => US [patent_app_date] => 2011-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6623 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13581298 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/581298
Battery system and control method of battery system Jun 6, 2011 Issued
Array ( [id] => 7493385 [patent_doc_number] => 20110239177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'METHOD AND SYSTEM FOR APPROXIMATE PLACEMENT IN ELECTRONIC DESIGNS' [patent_app_type] => utility [patent_app_number] => 13/154417 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6652 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20110239177.pdf [firstpage_image] =>[orig_patent_app_number] => 13154417 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/154417
Method and system for approximate placement in electronic designs Jun 5, 2011 Issued
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