Search

Ji H. Bae

Examiner (ID: 18876, Phone: (571)272-7181 , Office: P/2115 )

Most Active Art Unit
2115
Art Unit(s)
2187, 2115, 2118, 2176
Total Applications
984
Issued Applications
775
Pending Applications
53
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7671721 [patent_doc_number] => 20110320990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'LOGIC-DRIVEN LAYOUT VERIFICATION' [patent_app_type] => utility [patent_app_number] => 13/017788 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8842 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13017788 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/017788
Logic-driven layout verification Jan 30, 2011 Issued
Array ( [id] => 9392540 [patent_doc_number] => 08689165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Optimizing designs of integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/007579 [patent_app_country] => US [patent_app_date] => 2011-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7650 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13007579 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/007579
Optimizing designs of integrated circuits Jan 13, 2011 Issued
Array ( [id] => 8472873 [patent_doc_number] => 08302066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Clock jitter suppression method and computer-readable storage medium' [patent_app_type] => utility [patent_app_number] => 13/004577 [patent_app_country] => US [patent_app_date] => 2011-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7226 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13004577 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/004577
Clock jitter suppression method and computer-readable storage medium Jan 10, 2011 Issued
Array ( [id] => 9229892 [patent_doc_number] => 08635574 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-21 [patent_title] => 'Method and mechanism for implementing extraction for an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/987067 [patent_app_country] => US [patent_app_date] => 2011-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 5505 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12987067 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/987067
Method and mechanism for implementing extraction for an integrated circuit design Jan 6, 2011 Issued
Array ( [id] => 8615671 [patent_doc_number] => 20130020983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'RAPID CHARGER' [patent_app_type] => utility [patent_app_number] => 13/520348 [patent_app_country] => US [patent_app_date] => 2011-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 14210 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13520348 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/520348
RAPID CHARGER Jan 6, 2011 Abandoned
Array ( [id] => 9315093 [patent_doc_number] => 08656329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-18 [patent_title] => 'System and method for implementing power integrity topology adapted for parametrically integrated environment' [patent_app_type] => utility [patent_app_number] => 12/979137 [patent_app_country] => US [patent_app_date] => 2010-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 38 [patent_no_of_words] => 15723 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12979137 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/979137
System and method for implementing power integrity topology adapted for parametrically integrated environment Dec 26, 2010 Issued
Array ( [id] => 8193722 [patent_doc_number] => 20120119768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Method and System of Improved Reliability Testing' [patent_app_type] => utility [patent_app_number] => 12/948257 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6338 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119768.pdf [firstpage_image] =>[orig_patent_app_number] => 12948257 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/948257
Method and system of improved reliability testing Nov 16, 2010 Issued
Array ( [id] => 9289522 [patent_doc_number] => 08645880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Sum of coherent systems (SOCS) approximation based on object information' [patent_app_type] => utility [patent_app_number] => 12/945674 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5129 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12945674 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/945674
Sum of coherent systems (SOCS) approximation based on object information Nov 11, 2010 Issued
Array ( [id] => 8959172 [patent_doc_number] => 08504966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Method and device for reordering scan chains considering plan groups' [patent_app_type] => utility [patent_app_number] => 13/504051 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5980 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13504051 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/504051
Method and device for reordering scan chains considering plan groups Oct 26, 2010 Issued
Array ( [id] => 10600882 [patent_doc_number] => 09321433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Method for quickly supplying electric energy to electric vehicle and power supply device thereof' [patent_app_type] => utility [patent_app_number] => 13/511926 [patent_app_country] => US [patent_app_date] => 2010-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 47 [patent_no_of_words] => 18004 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13511926 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/511926
Method for quickly supplying electric energy to electric vehicle and power supply device thereof Oct 20, 2010 Issued
Array ( [id] => 8763390 [patent_doc_number] => 08423929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Intelligent architecture creator' [patent_app_type] => utility [patent_app_number] => 12/906857 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7717 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12906857 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906857
Intelligent architecture creator Oct 17, 2010 Issued
Array ( [id] => 8143733 [patent_doc_number] => 20120096419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'METHODOLOGY ON DEVELOPING METAL FILL AS LIBRARY DEVICE AND DESIGN STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/906707 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096419.pdf [firstpage_image] =>[orig_patent_app_number] => 12906707 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906707
Methodology on developing metal fill as library device and design structure Oct 17, 2010 Issued
Array ( [id] => 6040778 [patent_doc_number] => 20110093827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'SEMICONDUCTOR DEVICE DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 12/906117 [patent_app_country] => US [patent_app_date] => 2010-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11950 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20110093827.pdf [firstpage_image] =>[orig_patent_app_number] => 12906117 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906117
SEMICONDUCTOR DEVICE DESIGN METHOD Oct 16, 2010 Abandoned
Array ( [id] => 8763380 [patent_doc_number] => 08423919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Universal two-input logic gate that is configurable and connectable in an integrated circuit by a single mask layer adjustment' [patent_app_type] => utility [patent_app_number] => 12/853488 [patent_app_country] => US [patent_app_date] => 2010-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2417 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12853488 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/853488
Universal two-input logic gate that is configurable and connectable in an integrated circuit by a single mask layer adjustment Aug 9, 2010 Issued
Array ( [id] => 6645120 [patent_doc_number] => 20100313178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'CAD apparatus and check support apparatus' [patent_app_type] => utility [patent_app_number] => 12/805297 [patent_app_country] => US [patent_app_date] => 2010-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 8813 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20100313178.pdf [firstpage_image] =>[orig_patent_app_number] => 12805297 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/805297
CAD apparatus and check support apparatus Jul 21, 2010 Issued
Array ( [id] => 8912511 [patent_doc_number] => 08484588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'System, architecture and micro-architecture (SAMA) representation of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/835631 [patent_app_country] => US [patent_app_date] => 2010-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12835631 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/835631
System, architecture and micro-architecture (SAMA) representation of an integrated circuit Jul 12, 2010 Issued
Array ( [id] => 5933032 [patent_doc_number] => 20110041104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-17 [patent_title] => 'Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device' [patent_app_type] => utility [patent_app_number] => 12/805093 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14220 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20110041104.pdf [firstpage_image] =>[orig_patent_app_number] => 12805093 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/805093
Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device Jul 11, 2010 Abandoned
Array ( [id] => 6465006 [patent_doc_number] => 20100281454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'SYSTEM AND METHOD FOR INCLUDING PROTECTIVE VOLTAGE SWITCHABLE DIELECTRIC MATERIAL IN THE DESIGN OR SIMULATION OF SUBSTRATE DEVICES' [patent_app_type] => utility [patent_app_number] => 12/834296 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15556 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281454.pdf [firstpage_image] =>[orig_patent_app_number] => 12834296 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/834296
SYSTEM AND METHOD FOR INCLUDING PROTECTIVE VOLTAGE SWITCHABLE DIELECTRIC MATERIAL IN THE DESIGN OR SIMULATION OF SUBSTRATE DEVICES Jul 11, 2010 Abandoned
Array ( [id] => 6464995 [patent_doc_number] => 20100281453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'SYSTEM AND METHOD FOR INCLUDING PROTECTIVE VOLTAGE SWITCHABLE DIELECTRIC MATERIAL IN THE DESIGN OR SIMULATION OF SUBSTRATE DEVICES' [patent_app_type] => utility [patent_app_number] => 12/834273 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15558 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281453.pdf [firstpage_image] =>[orig_patent_app_number] => 12834273 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/834273
SYSTEM AND METHOD FOR INCLUDING PROTECTIVE VOLTAGE SWITCHABLE DIELECTRIC MATERIAL IN THE DESIGN OR SIMULATION OF SUBSTRATE DEVICES Jul 11, 2010 Abandoned
Array ( [id] => 7714305 [patent_doc_number] => 20120005547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'SCALABLE SYSTEM DEBUGGER FOR PROTOTYPE DEBUGGING' [patent_app_type] => utility [patent_app_number] => 12/827917 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4363 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005547.pdf [firstpage_image] =>[orig_patent_app_number] => 12827917 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827917
SCALABLE SYSTEM DEBUGGER FOR PROTOTYPE DEBUGGING Jun 29, 2010 Abandoned
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