Search

Jill E. Culler

Examiner (ID: 9368, Phone: (571)272-2159 , Office: P/2854 )

Most Active Art Unit
2854
Art Unit(s)
2854, 2853
Total Applications
1331
Issued Applications
816
Pending Applications
78
Abandoned Applications
459

Applications

Application numberTitle of the applicationFiling DateStatus
08/415515 FAST, DUAL PORTED CACHE CONTROLLER FOR DATA PROCESSORS IN A PACKET SWITCHED CACHE COHERENT MULTIPROCESSOR SYSTEM Mar 30, 1995 Abandoned
Array ( [id] => 3738369 [patent_doc_number] => 05652855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Memory circuit, method of access, and method of preparation of data in memory' [patent_app_type] => 1 [patent_app_number] => 8/412949 [patent_app_country] => US [patent_app_date] => 1995-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3581 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652855.pdf [firstpage_image] =>[orig_patent_app_number] => 412949 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/412949
Memory circuit, method of access, and method of preparation of data in memory Mar 28, 1995 Issued
Array ( [id] => 3588979 [patent_doc_number] => 05524230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'External information storage system with a semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/410589 [patent_app_country] => US [patent_app_date] => 1995-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7440 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524230.pdf [firstpage_image] =>[orig_patent_app_number] => 410589 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/410589
External information storage system with a semiconductor memory Mar 26, 1995 Issued
Array ( [id] => 3601364 [patent_doc_number] => 05517633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'System for controlling an internally-installed cache memory' [patent_app_type] => 1 [patent_app_number] => 8/406785 [patent_app_country] => US [patent_app_date] => 1995-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5576 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517633.pdf [firstpage_image] =>[orig_patent_app_number] => 406785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/406785
System for controlling an internally-installed cache memory Mar 19, 1995 Issued
Array ( [id] => 3708678 [patent_doc_number] => 05619679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Memory control device and method operated in consecutive access mode' [patent_app_type] => 1 [patent_app_number] => 8/396110 [patent_app_country] => US [patent_app_date] => 1995-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 61 [patent_no_of_words] => 19853 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619679.pdf [firstpage_image] =>[orig_patent_app_number] => 396110 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/396110
Memory control device and method operated in consecutive access mode Feb 27, 1995 Issued
Array ( [id] => 3694470 [patent_doc_number] => 05634031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Optical disk system having table-of-contents information data' [patent_app_type] => 1 [patent_app_number] => 8/391550 [patent_app_country] => US [patent_app_date] => 1995-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634031.pdf [firstpage_image] =>[orig_patent_app_number] => 391550 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/391550
Optical disk system having table-of-contents information data Feb 20, 1995 Issued
Array ( [id] => 3575894 [patent_doc_number] => 05526509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation' [patent_app_type] => 1 [patent_app_number] => 8/386757 [patent_app_country] => US [patent_app_date] => 1995-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 8571 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526509.pdf [firstpage_image] =>[orig_patent_app_number] => 386757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/386757
Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation Feb 9, 1995 Issued
Array ( [id] => 3600163 [patent_doc_number] => 05497478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles' [patent_app_type] => 1 [patent_app_number] => 8/381465 [patent_app_country] => US [patent_app_date] => 1995-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2853 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/497/05497478.pdf [firstpage_image] =>[orig_patent_app_number] => 381465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/381465
Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles Jan 30, 1995 Issued
Array ( [id] => 3636579 [patent_doc_number] => 05603005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed' [patent_app_type] => 1 [patent_app_number] => 8/364760 [patent_app_country] => US [patent_app_date] => 1994-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 16495 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603005.pdf [firstpage_image] =>[orig_patent_app_number] => 364760 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/364760
Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed Dec 26, 1994 Issued
Array ( [id] => 3544340 [patent_doc_number] => 05584013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache' [patent_app_type] => 1 [patent_app_number] => 8/353010 [patent_app_country] => US [patent_app_date] => 1994-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4794 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584013.pdf [firstpage_image] =>[orig_patent_app_number] => 353010 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/353010
Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache Dec 8, 1994 Issued
08/340740 HARDWARE ASSISTED DYNAMIC ACCESS ORDERING Nov 15, 1994 Abandoned
Array ( [id] => 3592492 [patent_doc_number] => 05499355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Prefetching into a cache to minimize main memory access time and cache size in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/339920 [patent_app_country] => US [patent_app_date] => 1994-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4314 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/499/05499355.pdf [firstpage_image] =>[orig_patent_app_number] => 339920 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/339920
Prefetching into a cache to minimize main memory access time and cache size in a computer system Nov 14, 1994 Issued
Array ( [id] => 3603795 [patent_doc_number] => 05586301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Personal computer hard disk protection system' [patent_app_type] => 1 [patent_app_number] => 8/336450 [patent_app_country] => US [patent_app_date] => 1994-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 31 [patent_no_of_words] => 10669 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586301.pdf [firstpage_image] =>[orig_patent_app_number] => 336450 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/336450
Personal computer hard disk protection system Nov 8, 1994 Issued
Array ( [id] => 3544367 [patent_doc_number] => 05584015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Buffer memory management method, recording medium, and computer system incorporating same' [patent_app_type] => 1 [patent_app_number] => 8/284670 [patent_app_country] => US [patent_app_date] => 1994-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2394 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584015.pdf [firstpage_image] =>[orig_patent_app_number] => 284670 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/284670
Buffer memory management method, recording medium, and computer system incorporating same Oct 23, 1994 Issued
Array ( [id] => 3595928 [patent_doc_number] => 05581740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'System for reading CD ROM data from hard disks' [patent_app_type] => 1 [patent_app_number] => 8/317510 [patent_app_country] => US [patent_app_date] => 1994-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3156 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581740.pdf [firstpage_image] =>[orig_patent_app_number] => 317510 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317510
System for reading CD ROM data from hard disks Oct 3, 1994 Issued
Array ( [id] => 3544410 [patent_doc_number] => 05584018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Information memory apparatus having a plurality of disk drives and calculating and re-allocating data according to access frequency' [patent_app_type] => 1 [patent_app_number] => 8/305950 [patent_app_country] => US [patent_app_date] => 1994-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 4605 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584018.pdf [firstpage_image] =>[orig_patent_app_number] => 305950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/305950
Information memory apparatus having a plurality of disk drives and calculating and re-allocating data according to access frequency Sep 14, 1994 Issued
Array ( [id] => 3529761 [patent_doc_number] => 05506976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Branch cache' [patent_app_type] => 1 [patent_app_number] => 8/303230 [patent_app_country] => US [patent_app_date] => 1994-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4766 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506976.pdf [firstpage_image] =>[orig_patent_app_number] => 303230 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/303230
Branch cache Sep 7, 1994 Issued
Array ( [id] => 3532274 [patent_doc_number] => 05530836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Method and apparatus for multiple memory bank selection' [patent_app_type] => 1 [patent_app_number] => 8/289830 [patent_app_country] => US [patent_app_date] => 1994-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3224 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530836.pdf [firstpage_image] =>[orig_patent_app_number] => 289830 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/289830
Method and apparatus for multiple memory bank selection Aug 11, 1994 Issued
Array ( [id] => 3530487 [patent_doc_number] => 05577230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Apparatus and method for computer processing using an enhanced Harvard architecture utilizing dual memory buses and the arbitration for data/instruction fetch' [patent_app_type] => 1 [patent_app_number] => 8/288420 [patent_app_country] => US [patent_app_date] => 1994-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577230.pdf [firstpage_image] =>[orig_patent_app_number] => 288420 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/288420
Apparatus and method for computer processing using an enhanced Harvard architecture utilizing dual memory buses and the arbitration for data/instruction fetch Aug 9, 1994 Issued
Array ( [id] => 3596616 [patent_doc_number] => 05581785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Starting system of disk storage device and data reading/writing system of the same' [patent_app_type] => 1 [patent_app_number] => 8/278085 [patent_app_country] => US [patent_app_date] => 1994-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4545 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581785.pdf [firstpage_image] =>[orig_patent_app_number] => 278085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/278085
Starting system of disk storage device and data reading/writing system of the same Jul 19, 1994 Issued
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