Search

Jill E. Culler

Examiner (ID: 9368, Phone: (571)272-2159 , Office: P/2854 )

Most Active Art Unit
2854
Art Unit(s)
2854, 2853
Total Applications
1331
Issued Applications
816
Pending Applications
78
Abandoned Applications
459

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3579583 [patent_doc_number] => 05485598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Redundant disk array (raid) system utilizing separate cache memories for the host system and the check data' [patent_app_type] => 1 [patent_app_number] => 8/053100 [patent_app_country] => US [patent_app_date] => 1993-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5017 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485598.pdf [firstpage_image] =>[orig_patent_app_number] => 053100 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/053100
Redundant disk array (raid) system utilizing separate cache memories for the host system and the check data Apr 25, 1993 Issued
Array ( [id] => 3500313 [patent_doc_number] => 05475814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Self diagnosis of a SCSI controller through an I/O port for data transmission/data reception modes of operation' [patent_app_type] => 1 [patent_app_number] => 8/051220 [patent_app_country] => US [patent_app_date] => 1993-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2360 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475814.pdf [firstpage_image] =>[orig_patent_app_number] => 051220 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/051220
Self diagnosis of a SCSI controller through an I/O port for data transmission/data reception modes of operation Apr 22, 1993 Issued
Array ( [id] => 3094993 [patent_doc_number] => 05280599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Computer system with memory expansion function and expansion memory setting method' [patent_app_type] => 1 [patent_app_number] => 8/049663 [patent_app_country] => US [patent_app_date] => 1993-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3434 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280599.pdf [firstpage_image] =>[orig_patent_app_number] => 049663 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/049663
Computer system with memory expansion function and expansion memory setting method Apr 20, 1993 Issued
Array ( [id] => 3532823 [patent_doc_number] => 05490265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Late cancel method and apparatus for a high performance microprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/046630 [patent_app_country] => US [patent_app_date] => 1993-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3988 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490265.pdf [firstpage_image] =>[orig_patent_app_number] => 046630 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/046630
Late cancel method and apparatus for a high performance microprocessor system Apr 13, 1993 Issued
Array ( [id] => 3589019 [patent_doc_number] => 05524233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations' [patent_app_type] => 1 [patent_app_number] => 8/040680 [patent_app_country] => US [patent_app_date] => 1993-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9032 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524233.pdf [firstpage_image] =>[orig_patent_app_number] => 040680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/040680
Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations Mar 30, 1993 Issued
08/037240 METHOD AND APPARATUS FOR INCREASED PERFORMANCE FROM A MEMORY STREAM BUFFER BY ELIMINATING READ-MODIFY-WRITE STREAMS FROM HISTORY BUFFER Mar 25, 1993 Pending
Array ( [id] => 3432558 [patent_doc_number] => 05479641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking' [patent_app_type] => 1 [patent_app_number] => 8/035630 [patent_app_country] => US [patent_app_date] => 1993-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6778 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479641.pdf [firstpage_image] =>[orig_patent_app_number] => 035630 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/035630
Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking Mar 23, 1993 Issued
Array ( [id] => 3132931 [patent_doc_number] => 05450565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Circuit and method for selecting a set in a set associative cache' [patent_app_type] => 1 [patent_app_number] => 8/035740 [patent_app_country] => US [patent_app_date] => 1993-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6954 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450565.pdf [firstpage_image] =>[orig_patent_app_number] => 035740 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/035740
Circuit and method for selecting a set in a set associative cache Mar 22, 1993 Issued
Array ( [id] => 3041915 [patent_doc_number] => 05317720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Processor system with writeback cache using writeback and non writeback transactions stored in separate queues' [patent_app_type] => 1 [patent_app_number] => 8/034581 [patent_app_country] => US [patent_app_date] => 1993-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 45113 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/317/05317720.pdf [firstpage_image] =>[orig_patent_app_number] => 034581 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/034581
Processor system with writeback cache using writeback and non writeback transactions stored in separate queues Mar 21, 1993 Issued
Array ( [id] => 3024448 [patent_doc_number] => 05276852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions' [patent_app_type] => 1 [patent_app_number] => 8/032814 [patent_app_country] => US [patent_app_date] => 1993-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 10227 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276852.pdf [firstpage_image] =>[orig_patent_app_number] => 032814 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/032814
Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions Mar 14, 1993 Issued
Array ( [id] => 3566422 [patent_doc_number] => 05519842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Method and apparatus for performing unaligned little endian and big endian data accesses in a processing system' [patent_app_type] => 1 [patent_app_number] => 8/023560 [patent_app_country] => US [patent_app_date] => 1993-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2193 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519842.pdf [firstpage_image] =>[orig_patent_app_number] => 023560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/023560
Method and apparatus for performing unaligned little endian and big endian data accesses in a processing system Feb 25, 1993 Issued
Array ( [id] => 3600108 [patent_doc_number] => 05497474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Data stream addressing' [patent_app_type] => 1 [patent_app_number] => 8/023370 [patent_app_country] => US [patent_app_date] => 1993-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3410 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/497/05497474.pdf [firstpage_image] =>[orig_patent_app_number] => 023370 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/023370
Data stream addressing Feb 24, 1993 Issued
08/022760 APPARATUS AND METHOD TO SET AND RESET A PIPELINE INSTRUCTION EXECUTION CONTROL UNIT FOR SEQUENTIAL EXECUTION OF AN INSTRUCTION INTERVAL Feb 21, 1993 Abandoned
Array ( [id] => 3435172 [patent_doc_number] => 05459850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Flash solid state drive that emulates a disk drive and stores variable length and fixed lenth data blocks' [patent_app_type] => 1 [patent_app_number] => 8/019860 [patent_app_country] => US [patent_app_date] => 1993-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12484 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459850.pdf [firstpage_image] =>[orig_patent_app_number] => 019860 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/019860
Flash solid state drive that emulates a disk drive and stores variable length and fixed lenth data blocks Feb 18, 1993 Issued
Array ( [id] => 3579488 [patent_doc_number] => 05485591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Microprocessor wherein the number of register output signal liner connected to the buses are reduced reducing the load capacity of the buses' [patent_app_type] => 1 [patent_app_number] => 8/018870 [patent_app_country] => US [patent_app_date] => 1993-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3228 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485591.pdf [firstpage_image] =>[orig_patent_app_number] => 018870 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/018870
Microprocessor wherein the number of register output signal liner connected to the buses are reduced reducing the load capacity of the buses Feb 16, 1993 Issued
Array ( [id] => 3089983 [patent_doc_number] => 05297270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Programmable cache memory which associates each section of main memory to be cached with a status bit which enables/disables the caching accessibility of the particular section, and with the capability of functioning with memory areas of varying size' [patent_app_type] => 1 [patent_app_number] => 8/017972 [patent_app_country] => US [patent_app_date] => 1993-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5303 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297270.pdf [firstpage_image] =>[orig_patent_app_number] => 017972 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/017972
Programmable cache memory which associates each section of main memory to be cached with a status bit which enables/disables the caching accessibility of the particular section, and with the capability of functioning with memory areas of varying size Feb 11, 1993 Issued
Array ( [id] => 3533850 [patent_doc_number] => 05530938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Non-volatile memory card device having flash EEPROM memory chips with designated spare memory chips and the method of rewriting data into the memory card device' [patent_app_type] => 1 [patent_app_number] => 8/014430 [patent_app_country] => US [patent_app_date] => 1993-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3432 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530938.pdf [firstpage_image] =>[orig_patent_app_number] => 014430 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/014430
Non-volatile memory card device having flash EEPROM memory chips with designated spare memory chips and the method of rewriting data into the memory card device Feb 4, 1993 Issued
08/014064 LEAST RECENTLY USED REPLACEMENT APPARATUS FOR A SYSTEM WITH A SET ASSOCIATIVE CACHE Feb 4, 1993 Abandoned
Array ( [id] => 3626339 [patent_doc_number] => 05535362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Data transfer control apparatus wherein a time value is compared to a clocked timer value with a comparison of the values causing the transfer of bus use right' [patent_app_type] => 1 [patent_app_number] => 8/013450 [patent_app_country] => US [patent_app_date] => 1993-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4028 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535362.pdf [firstpage_image] =>[orig_patent_app_number] => 013450 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/013450
Data transfer control apparatus wherein a time value is compared to a clocked timer value with a comparison of the values causing the transfer of bus use right Feb 3, 1993 Issued
Array ( [id] => 3585649 [patent_doc_number] => 05539898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Data-array processing system wherein parallel processors access to the memory system is optimized' [patent_app_type] => 1 [patent_app_number] => 8/110180 [patent_app_country] => US [patent_app_date] => 1993-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 74 [patent_no_of_words] => 23349 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539898.pdf [firstpage_image] =>[orig_patent_app_number] => 110180 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/110180
Data-array processing system wherein parallel processors access to the memory system is optimized Jan 31, 1993 Issued
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