Search

Jimmy Chou

Examiner (ID: 14719, Phone: (571)270-7107 , Office: P/3742 )

Most Active Art Unit
3761
Art Unit(s)
3761, 3742
Total Applications
974
Issued Applications
646
Pending Applications
108
Abandoned Applications
256

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7022942 [patent_doc_number] => 20050017336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => '[MULTI-CHIP PACKAGE]' [patent_app_type] => utility [patent_app_number] => 10/709925 [patent_app_country] => US [patent_app_date] => 2004-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4303 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017336.pdf [firstpage_image] =>[orig_patent_app_number] => 10709925 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709925
[MULTI-CHIP PACKAGE] Jun 6, 2004 Abandoned
Array ( [id] => 7250038 [patent_doc_number] => 20040238878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Manufacturing method of a semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/854315 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12103 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20040238878.pdf [firstpage_image] =>[orig_patent_app_number] => 10854315 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/854315
Manufacturing method of a semiconductor integrated circuit device May 26, 2004 Abandoned
Array ( [id] => 5765910 [patent_doc_number] => 20050263901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'SEMICONDUCTOR DEVICE FORMED BY IN-SITU MODIFICATION OF DIELECTRIC LAYER AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 10/709776 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20050263901.pdf [firstpage_image] =>[orig_patent_app_number] => 10709776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709776
SEMICONDUCTOR DEVICE FORMED BY IN-SITU MODIFICATION OF DIELECTRIC LAYER AND RELATED METHODS May 26, 2004 Abandoned
Array ( [id] => 7411848 [patent_doc_number] => 20040207063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Semiconductor component in a wafer assembly' [patent_app_type] => new [patent_app_number] => 10/845848 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2159 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20040207063.pdf [firstpage_image] =>[orig_patent_app_number] => 10845848 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/845848
Semiconductor component in a wafer assembly May 13, 2004 Abandoned
Array ( [id] => 7067057 [patent_doc_number] => 20050242439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'METHOD AND STRUCTURE FOR CONNECTING GROUND/POWER NETWORKS TO PREVENT CHARGE DAMAGE IN SILICON ON INSULATOR' [patent_app_type] => utility [patent_app_number] => 10/709325 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20050242439.pdf [firstpage_image] =>[orig_patent_app_number] => 10709325 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709325
METHOD AND STRUCTURE FOR CONNECTING GROUND/POWER NETWORKS TO PREVENT CHARGE DAMAGE IN SILICON ON INSULATOR Apr 27, 2004 Abandoned
Array ( [id] => 6963828 [patent_doc_number] => 20050230725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Ferroelectric capacitor having an oxide electrode template and a method of manufacture therefor' [patent_app_type] => utility [patent_app_number] => 10/828446 [patent_app_country] => US [patent_app_date] => 2004-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5130 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20050230725.pdf [firstpage_image] =>[orig_patent_app_number] => 10828446 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/828446
Ferroelectric capacitor having an oxide electrode template and a method of manufacture therefor Apr 19, 2004 Abandoned
Array ( [id] => 7291850 [patent_doc_number] => 20040212087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'WIRING SUBSTRATE AND ELECTRONIC PARTS PACKAGING STRUCTURE' [patent_app_type] => new [patent_app_number] => 10/709096 [patent_app_country] => US [patent_app_date] => 2004-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4580 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212087.pdf [firstpage_image] =>[orig_patent_app_number] => 10709096 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709096
Wiring substrate and electronic parts packaging structure Apr 12, 2004 Issued
Array ( [id] => 345466 [patent_doc_number] => 07498656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Electromagnetic shielding structure' [patent_app_type] => utility [patent_app_number] => 10/813886 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 7541 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/498/07498656.pdf [firstpage_image] =>[orig_patent_app_number] => 10813886 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/813886
Electromagnetic shielding structure Mar 30, 2004 Issued
Array ( [id] => 7108559 [patent_doc_number] => 20050206012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Stress and force management techniques for a semiconductor die' [patent_app_type] => utility [patent_app_number] => 10/801205 [patent_app_country] => US [patent_app_date] => 2004-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5998 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20050206012.pdf [firstpage_image] =>[orig_patent_app_number] => 10801205 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/801205
Stress and force management techniques for a semiconductor die Mar 15, 2004 Abandoned
Array ( [id] => 7140173 [patent_doc_number] => 20050116324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/798555 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6799 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20050116324.pdf [firstpage_image] =>[orig_patent_app_number] => 10798555 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798555
Semiconductor device and manufacturing method thereof Mar 11, 2004 Issued
Array ( [id] => 7176797 [patent_doc_number] => 20050189656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Micro-vias for electronic packaging' [patent_app_type] => utility [patent_app_number] => 10/787625 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 865 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20050189656.pdf [firstpage_image] =>[orig_patent_app_number] => 10787625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/787625
Micro-vias for electronic packaging Feb 25, 2004 Abandoned
Array ( [id] => 7415256 [patent_doc_number] => 20040159945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Underfill process for flip-chip device' [patent_app_type] => new [patent_app_number] => 10/774869 [patent_app_country] => US [patent_app_date] => 2004-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3797 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20040159945.pdf [firstpage_image] =>[orig_patent_app_number] => 10774869 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/774869
Underfill process for flip-chip device Feb 8, 2004 Abandoned
Array ( [id] => 480230 [patent_doc_number] => 07224060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Integrated circuit with protective moat' [patent_app_type] => utility [patent_app_number] => 10/768796 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2926 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224060.pdf [firstpage_image] =>[orig_patent_app_number] => 10768796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/768796
Integrated circuit with protective moat Jan 29, 2004 Issued
Array ( [id] => 7407081 [patent_doc_number] => 20040227176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Voltage-variable capacitor with increased current conducting perimeter' [patent_app_type] => new [patent_app_number] => 10/765578 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6380 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20040227176.pdf [firstpage_image] =>[orig_patent_app_number] => 10765578 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/765578
Voltage-variable capacitor with increased current conducting perimeter Jan 25, 2004 Abandoned
Array ( [id] => 7421212 [patent_doc_number] => 20040183180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Multi-chips stacked package' [patent_app_type] => new [patent_app_number] => 10/747036 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183180.pdf [firstpage_image] =>[orig_patent_app_number] => 10747036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747036
Multi-chips stacked package Dec 29, 2003 Abandoned
Array ( [id] => 7236636 [patent_doc_number] => 20050139991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Thermal intermediate apparatus, systems, and methods' [patent_app_type] => utility [patent_app_number] => 10/748565 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3248 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20050139991.pdf [firstpage_image] =>[orig_patent_app_number] => 10748565 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748565
Thermal intermediate apparatus, systems, and methods Dec 29, 2003 Issued
Array ( [id] => 7291827 [patent_doc_number] => 20040212066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Multi-chips stacked package' [patent_app_type] => new [patent_app_number] => 10/747316 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2092 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212066.pdf [firstpage_image] =>[orig_patent_app_number] => 10747316 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747316
Multi-chips stacked package Dec 29, 2003 Abandoned
Array ( [id] => 8555783 [patent_doc_number] => 08330258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'System and method for improving solder joint reliability in an integrated circuit package' [patent_app_type] => utility [patent_app_number] => 10/746745 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4357 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10746745 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746745
System and method for improving solder joint reliability in an integrated circuit package Dec 23, 2003 Issued
Array ( [id] => 6994131 [patent_doc_number] => 20050133907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Mechanism for maintaining consistent thermal interface layer in an integrated circuit assembly' [patent_app_type] => utility [patent_app_number] => 10/744835 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20050133907.pdf [firstpage_image] =>[orig_patent_app_number] => 10744835 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744835
Mechanism for maintaining consistent thermal interface layer in an integrated circuit assembly Dec 22, 2003 Abandoned
Array ( [id] => 6994127 [patent_doc_number] => 20050133903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Integrated circuit package substrate having a thin film capacitor structure' [patent_app_type] => utility [patent_app_number] => 10/746665 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2267 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20050133903.pdf [firstpage_image] =>[orig_patent_app_number] => 10746665 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746665
Integrated circuit package substrate having a thin film capacitor structure Dec 22, 2003 Issued
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