
Jimmy Chou
Examiner (ID: 14719, Phone: (571)270-7107 , Office: P/3742 )
| Most Active Art Unit | 3761 |
| Art Unit(s) | 3761, 3742 |
| Total Applications | 974 |
| Issued Applications | 646 |
| Pending Applications | 108 |
| Abandoned Applications | 256 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7022942
[patent_doc_number] => 20050017336
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-27
[patent_title] => '[MULTI-CHIP PACKAGE]'
[patent_app_type] => utility
[patent_app_number] => 10/709925
[patent_app_country] => US
[patent_app_date] => 2004-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4303
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[patent_maintenance] => 1
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[pdf_file] => publications/A1/0017/20050017336.pdf
[firstpage_image] =>[orig_patent_app_number] => 10709925
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709925 | [MULTI-CHIP PACKAGE] | Jun 6, 2004 | Abandoned |
Array
(
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[patent_doc_number] => 20040238878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Manufacturing method of a semiconductor integrated circuit device'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/854315 | Manufacturing method of a semiconductor integrated circuit device | May 26, 2004 | Abandoned |
Array
(
[id] => 5765910
[patent_doc_number] => 20050263901
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-01
[patent_title] => 'SEMICONDUCTOR DEVICE FORMED BY IN-SITU MODIFICATION OF DIELECTRIC LAYER AND RELATED METHODS'
[patent_app_type] => utility
[patent_app_number] => 10/709776
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709776 | SEMICONDUCTOR DEVICE FORMED BY IN-SITU MODIFICATION OF DIELECTRIC LAYER AND RELATED METHODS | May 26, 2004 | Abandoned |
Array
(
[id] => 7411848
[patent_doc_number] => 20040207063
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Semiconductor component in a wafer assembly'
[patent_app_type] => new
[patent_app_number] => 10/845848
[patent_app_country] => US
[patent_app_date] => 2004-05-14
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Array
(
[id] => 7067057
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[patent_issue_date] => 2005-11-03
[patent_title] => 'METHOD AND STRUCTURE FOR CONNECTING GROUND/POWER NETWORKS TO PREVENT CHARGE DAMAGE IN SILICON ON INSULATOR'
[patent_app_type] => utility
[patent_app_number] => 10/709325
[patent_app_country] => US
[patent_app_date] => 2004-04-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709325 | METHOD AND STRUCTURE FOR CONNECTING GROUND/POWER NETWORKS TO PREVENT CHARGE DAMAGE IN SILICON ON INSULATOR | Apr 27, 2004 | Abandoned |
Array
(
[id] => 6963828
[patent_doc_number] => 20050230725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-20
[patent_title] => 'Ferroelectric capacitor having an oxide electrode template and a method of manufacture therefor'
[patent_app_type] => utility
[patent_app_number] => 10/828446
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/828446 | Ferroelectric capacitor having an oxide electrode template and a method of manufacture therefor | Apr 19, 2004 | Abandoned |
Array
(
[id] => 7291850
[patent_doc_number] => 20040212087
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'WIRING SUBSTRATE AND ELECTRONIC PARTS PACKAGING STRUCTURE'
[patent_app_type] => new
[patent_app_number] => 10/709096
[patent_app_country] => US
[patent_app_date] => 2004-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0212/20040212087.pdf
[firstpage_image] =>[orig_patent_app_number] => 10709096
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709096 | Wiring substrate and electronic parts packaging structure | Apr 12, 2004 | Issued |
Array
(
[id] => 345466
[patent_doc_number] => 07498656
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-03
[patent_title] => 'Electromagnetic shielding structure'
[patent_app_type] => utility
[patent_app_number] => 10/813886
[patent_app_country] => US
[patent_app_date] => 2004-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[firstpage_image] =>[orig_patent_app_number] => 10813886
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/813886 | Electromagnetic shielding structure | Mar 30, 2004 | Issued |
Array
(
[id] => 7108559
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[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'Stress and force management techniques for a semiconductor die'
[patent_app_type] => utility
[patent_app_number] => 10/801205
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[patent_app_date] => 2004-03-16
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[pdf_file] => publications/A1/0206/20050206012.pdf
[firstpage_image] =>[orig_patent_app_number] => 10801205
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/801205 | Stress and force management techniques for a semiconductor die | Mar 15, 2004 | Abandoned |
Array
(
[id] => 7140173
[patent_doc_number] => 20050116324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/798555
[patent_app_country] => US
[patent_app_date] => 2004-03-12
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[firstpage_image] =>[orig_patent_app_number] => 10798555
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/798555 | Semiconductor device and manufacturing method thereof | Mar 11, 2004 | Issued |
Array
(
[id] => 7176797
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[patent_country] => US
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[patent_issue_date] => 2005-09-01
[patent_title] => 'Micro-vias for electronic packaging'
[patent_app_type] => utility
[patent_app_number] => 10/787625
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/787625 | Micro-vias for electronic packaging | Feb 25, 2004 | Abandoned |
Array
(
[id] => 7415256
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Array
(
[id] => 480230
[patent_doc_number] => 07224060
[patent_country] => US
[patent_kind] => B2
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[patent_title] => 'Integrated circuit with protective moat'
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Array
(
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[patent_title] => 'Voltage-variable capacitor with increased current conducting perimeter'
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Array
(
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Array
(
[id] => 7236636
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Array
(
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Array
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746665 | Integrated circuit package substrate having a thin film capacitor structure | Dec 22, 2003 | Issued |