Search

Jimmy Chou

Examiner (ID: 14719, Phone: (571)270-7107 , Office: P/3742 )

Most Active Art Unit
3761
Art Unit(s)
3761, 3742
Total Applications
974
Issued Applications
646
Pending Applications
108
Abandoned Applications
256

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6994157 [patent_doc_number] => 20050133933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Various structure/height bumps for wafer level-chip scale package' [patent_app_type] => utility [patent_app_number] => 10/742306 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3403 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20050133933.pdf [firstpage_image] =>[orig_patent_app_number] => 10742306 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/742306
Various structure/height bumps for wafer level-chip scale package Dec 18, 2003 Abandoned
Array ( [id] => 7393818 [patent_doc_number] => 20040173898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Semiconductor apparatus having system-in-package arrangement with improved heat dissipation' [patent_app_type] => new [patent_app_number] => 10/739536 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3620 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20040173898.pdf [firstpage_image] =>[orig_patent_app_number] => 10739536 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739536
Semiconductor apparatus having system-in-package arrangement with improved heat dissipation Dec 18, 2003 Abandoned
Array ( [id] => 7094897 [patent_doc_number] => 20050127500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Local reduction of compliant thermally conductive material layer thickness on chips' [patent_app_type] => utility [patent_app_number] => 10/732015 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127500.pdf [firstpage_image] =>[orig_patent_app_number] => 10732015 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/732015
Local reduction of compliant thermally conductive material layer thickness on chips Dec 9, 2003 Abandoned
Array ( [id] => 7456985 [patent_doc_number] => 20040119137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Resistive structure integrated in a semiconductor substrate' [patent_app_type] => new [patent_app_number] => 10/729721 [patent_app_country] => US [patent_app_date] => 2003-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4260 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20040119137.pdf [firstpage_image] =>[orig_patent_app_number] => 10729721 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/729721
Resistive structure integrated in a semiconductor substrate Dec 4, 2003 Abandoned
Array ( [id] => 7169173 [patent_doc_number] => 20050121757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Integrated circuit package overlay' [patent_app_type] => utility [patent_app_number] => 10/728245 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2172 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121757.pdf [firstpage_image] =>[orig_patent_app_number] => 10728245 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728245
Integrated circuit package overlay Dec 3, 2003 Abandoned
Array ( [id] => 7260393 [patent_doc_number] => 20040150097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'OPTIMIZED CONDUCTIVE LID MOUNTING FOR INTEGRATED CIRCUIT CHIP CARRIERS' [patent_app_type] => new [patent_app_number] => 10/707206 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150097.pdf [firstpage_image] =>[orig_patent_app_number] => 10707206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707206
OPTIMIZED CONDUCTIVE LID MOUNTING FOR INTEGRATED CIRCUIT CHIP CARRIERS Nov 25, 2003 Abandoned
Array ( [id] => 6936576 [patent_doc_number] => 20050110137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Plastic dual-in-line packaging (PDIP) having enhanced heat dissipation' [patent_app_type] => utility [patent_app_number] => 10/723036 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3383 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110137.pdf [firstpage_image] =>[orig_patent_app_number] => 10723036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/723036
Plastic dual-in-line packaging (PDIP) having enhanced heat dissipation Nov 24, 2003 Abandoned
Array ( [id] => 7101491 [patent_doc_number] => 20050104217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'SEEDLESS WIREBOND PAD PLATING' [patent_app_type] => utility [patent_app_number] => 10/707075 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2716 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104217.pdf [firstpage_image] =>[orig_patent_app_number] => 10707075 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707075
Seedless wirebond pad plating Nov 18, 2003 Issued
Array ( [id] => 7451744 [patent_doc_number] => 20040099935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Electronic package with snap-on perimeter wall' [patent_app_type] => new [patent_app_number] => 10/714726 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20040099935.pdf [firstpage_image] =>[orig_patent_app_number] => 10714726 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714726
Electronic package with snap-on perimeter wall Nov 16, 2003 Issued
Array ( [id] => 7421146 [patent_doc_number] => 20040183167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Recessed-bond semiconductor package substrate' [patent_app_type] => new [patent_app_number] => 10/714285 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4978 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183167.pdf [firstpage_image] =>[orig_patent_app_number] => 10714285 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714285
Recessed-bond semiconductor package substrate Nov 13, 2003 Abandoned
Array ( [id] => 7101445 [patent_doc_number] => 20050104171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Microelectronic devices having conductive complementary structures and methods of manufacturing microelectronic devices having conductive complementary structures' [patent_app_type] => utility [patent_app_number] => 10/713626 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5255 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104171.pdf [firstpage_image] =>[orig_patent_app_number] => 10713626 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713626
Microelectronic devices having conductive complementary structures and methods of manufacturing microelectronic devices having conductive complementary structures Nov 12, 2003 Abandoned
Array ( [id] => 33748 [patent_doc_number] => 07791210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Semiconductor package having discrete non-active electrical components incorporated into the package' [patent_app_type] => utility [patent_app_number] => 10/702996 [patent_app_country] => US [patent_app_date] => 2003-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4511 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791210.pdf [firstpage_image] =>[orig_patent_app_number] => 10702996 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/702996
Semiconductor package having discrete non-active electrical components incorporated into the package Nov 4, 2003 Issued
Array ( [id] => 7295967 [patent_doc_number] => 20040124516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Circuit device, circuit module, and method for manufacturing circuit device' [patent_app_type] => new [patent_app_number] => 10/701915 [patent_app_country] => US [patent_app_date] => 2003-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6056 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124516.pdf [firstpage_image] =>[orig_patent_app_number] => 10701915 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/701915
Circuit device, circuit module, and method for manufacturing circuit device Nov 4, 2003 Abandoned
Array ( [id] => 7195333 [patent_doc_number] => 20040085795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Memory module and memory configuration with stub-free signal lines and distributed capacitive loads' [patent_app_type] => new [patent_app_number] => 10/695366 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3700 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20040085795.pdf [firstpage_image] =>[orig_patent_app_number] => 10695366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695366
Memory module and memory configuration with stub-free signal lines and distributed capacitive loads Oct 27, 2003 Abandoned
Array ( [id] => 7295963 [patent_doc_number] => 20040124512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Thermal enhance MCM package' [patent_app_type] => new [patent_app_number] => 10/693976 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2027 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124512.pdf [firstpage_image] =>[orig_patent_app_number] => 10693976 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/693976
Thermal enhance MCM package Oct 27, 2003 Abandoned
Array ( [id] => 6988755 [patent_doc_number] => 20050087856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Electromagnetic noise shielding in semiconductor packages using caged interconnect structures' [patent_app_type] => utility [patent_app_number] => 10/694146 [patent_app_country] => US [patent_app_date] => 2003-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4167 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20050087856.pdf [firstpage_image] =>[orig_patent_app_number] => 10694146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/694146
Electromagnetic noise shielding in semiconductor packages using caged interconnect structures Oct 26, 2003 Issued
Array ( [id] => 6988811 [patent_doc_number] => 20050087884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Flip-chip light emitting diode' [patent_app_type] => utility [patent_app_number] => 10/693126 [patent_app_country] => US [patent_app_date] => 2003-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4706 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20050087884.pdf [firstpage_image] =>[orig_patent_app_number] => 10693126 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/693126
Flip-chip light emitting diode Oct 23, 2003 Issued
Array ( [id] => 7459503 [patent_doc_number] => 20040094827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Leadframe for semiconductor device, method for manufacturing semiconductor device using the same, semiconductor device using the same, and electronic equipment' [patent_app_type] => new [patent_app_number] => 10/690615 [patent_app_country] => US [patent_app_date] => 2003-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4498 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20040094827.pdf [firstpage_image] =>[orig_patent_app_number] => 10690615 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/690615
Leadframe for semiconductor device, method for manufacturing semiconductor device using the same, semiconductor device using the same, and electronic equipment Oct 22, 2003 Abandoned
Array ( [id] => 7295971 [patent_doc_number] => 20040124520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Stacked electronic structures including offset substrates' [patent_app_type] => new [patent_app_number] => 10/689976 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8289 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124520.pdf [firstpage_image] =>[orig_patent_app_number] => 10689976 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/689976
Stacked electronic structures including offset substrates Oct 20, 2003 Issued
Array ( [id] => 5790969 [patent_doc_number] => 20060012023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Method of manufacturing a data carrier' [patent_app_type] => utility [patent_app_number] => 10/531365 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1358 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20060012023.pdf [firstpage_image] =>[orig_patent_app_number] => 10531365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/531365
Method of manufacturing a data carrier Oct 14, 2003 Issued
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