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Jimmy Nguyen

Examiner (ID: 7143)

Most Active Art Unit
2829
Art Unit(s)
2858, 2829
Total Applications
440
Issued Applications
398
Pending Applications
9
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6881843 [patent_doc_number] => 20010048315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Apparatus for measuring thermal properties and making thermomechanical modification on sample surface with peltier tip' [patent_app_type] => new [patent_app_number] => 09/851319 [patent_app_country] => US [patent_app_date] => 2001-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2154 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048315.pdf [firstpage_image] =>[orig_patent_app_number] => 09851319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/851319
Apparatus for measuring thermal properties and making thermomechanical modification on sample surface with peltier tip May 8, 2001 Issued
Array ( [id] => 1425570 [patent_doc_number] => 06507209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Tester accuracy using multiple passes' [patent_app_type] => B1 [patent_app_number] => 09/850806 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2997 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507209.pdf [firstpage_image] =>[orig_patent_app_number] => 09850806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/850806
Tester accuracy using multiple passes May 7, 2001 Issued
Array ( [id] => 1232979 [patent_doc_number] => 06693449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Circuit and method for determining the operating point of a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/851512 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693449.pdf [firstpage_image] =>[orig_patent_app_number] => 09851512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/851512
Circuit and method for determining the operating point of a semiconductor device May 7, 2001 Issued
Array ( [id] => 6998696 [patent_doc_number] => 20010052782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'BGA on-board tester' [patent_app_type] => new [patent_app_number] => 09/851490 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3542 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20010052782.pdf [firstpage_image] =>[orig_patent_app_number] => 09851490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/851490
BGA on-board tester May 7, 2001 Issued
Array ( [id] => 1381961 [patent_doc_number] => 06563301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Advanced production test method and apparatus for testing electronic devices' [patent_app_type] => B2 [patent_app_number] => 09/845912 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3818 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563301.pdf [firstpage_image] =>[orig_patent_app_number] => 09845912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845912
Advanced production test method and apparatus for testing electronic devices Apr 29, 2001 Issued
Array ( [id] => 1598375 [patent_doc_number] => 06492830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method and circuit for measuring charge dump of an individual transistor in an SOI device' [patent_app_type] => B1 [patent_app_number] => 09/845860 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4016 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492830.pdf [firstpage_image] =>[orig_patent_app_number] => 09845860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845860
Method and circuit for measuring charge dump of an individual transistor in an SOI device Apr 29, 2001 Issued
Array ( [id] => 1413147 [patent_doc_number] => 06535015 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Device and method for testing performance of silicon structures' [patent_app_type] => B1 [patent_app_number] => 09/845266 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3188 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535015.pdf [firstpage_image] =>[orig_patent_app_number] => 09845266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845266
Device and method for testing performance of silicon structures Apr 29, 2001 Issued
Array ( [id] => 1151682 [patent_doc_number] => 06774658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Device testing using a holding-circuit' [patent_app_type] => B2 [patent_app_number] => 09/843606 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774658.pdf [firstpage_image] =>[orig_patent_app_number] => 09843606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/843606
Device testing using a holding-circuit Apr 25, 2001 Issued
Array ( [id] => 1389340 [patent_doc_number] => 06556035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Test key layout for detecting via-open failure' [patent_app_type] => B2 [patent_app_number] => 09/843408 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2452 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556035.pdf [firstpage_image] =>[orig_patent_app_number] => 09843408 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/843408
Test key layout for detecting via-open failure Apr 25, 2001 Issued
Array ( [id] => 6447698 [patent_doc_number] => 20020149384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Test probe including control device' [patent_app_type] => new [patent_app_number] => 09/834249 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2012 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149384.pdf [firstpage_image] =>[orig_patent_app_number] => 09834249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/834249
Test probe including control device Apr 10, 2001 Abandoned
Array ( [id] => 1381936 [patent_doc_number] => 06563300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method and apparatus for fault detection using multiple tool error signals' [patent_app_type] => B1 [patent_app_number] => 09/832781 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4005 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563300.pdf [firstpage_image] =>[orig_patent_app_number] => 09832781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832781
Method and apparatus for fault detection using multiple tool error signals Apr 10, 2001 Issued
Array ( [id] => 1133381 [patent_doc_number] => 06788090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Method and apparatus for inspecting semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/832666 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4960 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788090.pdf [firstpage_image] =>[orig_patent_app_number] => 09832666 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832666
Method and apparatus for inspecting semiconductor device Apr 10, 2001 Issued
Array ( [id] => 6447739 [patent_doc_number] => 20020149388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Method for the accurate electrical testing of semiconductor devices' [patent_app_type] => new [patent_app_number] => 09/833462 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3656 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149388.pdf [firstpage_image] =>[orig_patent_app_number] => 09833462 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/833462
Method for the accurate electrical testing of semiconductor devices Apr 10, 2001 Abandoned
Array ( [id] => 1456146 [patent_doc_number] => 06462572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-08 [patent_title] => 'Socket used for semiconductor device and testing system connected to socket through dual-transmission lines' [patent_app_type] => B2 [patent_app_number] => 09/815550 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5673 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/462/06462572.pdf [firstpage_image] =>[orig_patent_app_number] => 09815550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/815550
Socket used for semiconductor device and testing system connected to socket through dual-transmission lines Mar 21, 2001 Issued
Array ( [id] => 6510743 [patent_doc_number] => 20020135389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Wafer-level burn-in oven' [patent_app_type] => new [patent_app_number] => 09/813074 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6469 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20020135389.pdf [firstpage_image] =>[orig_patent_app_number] => 09813074 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813074
Wafer-level burn-in oven Mar 19, 2001 Issued
Array ( [id] => 1393709 [patent_doc_number] => 06552525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'System and method for scheduling and monitoring electrical device usage' [patent_app_type] => B2 [patent_app_number] => 09/681290 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2093 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552525.pdf [firstpage_image] =>[orig_patent_app_number] => 09681290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681290
System and method for scheduling and monitoring electrical device usage Mar 13, 2001 Issued
Array ( [id] => 6368334 [patent_doc_number] => 20020118031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Connector test card' [patent_app_type] => new [patent_app_number] => 09/794602 [patent_app_country] => US [patent_app_date] => 2001-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4176 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20020118031.pdf [firstpage_image] =>[orig_patent_app_number] => 09794602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794602
Connector test card Feb 26, 2001 Abandoned
Array ( [id] => 1292037 [patent_doc_number] => 06633177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method of predicting lifetime of semiconductor integrated circuit and method for reliability testing of the circuit' [patent_app_type] => B1 [patent_app_number] => 09/744260 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10604 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633177.pdf [firstpage_image] =>[orig_patent_app_number] => 09744260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/744260
Method of predicting lifetime of semiconductor integrated circuit and method for reliability testing of the circuit Jan 31, 2001 Issued
Array ( [id] => 6877308 [patent_doc_number] => 20010002794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-07 [patent_title] => 'Split resistor probe and method' [patent_app_type] => new-utility [patent_app_number] => 09/774195 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4894 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002794.pdf [firstpage_image] =>[orig_patent_app_number] => 09774195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774195
Split resistor probe and method Jan 28, 2001 Issued
Array ( [id] => 6012958 [patent_doc_number] => 20020101255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method and apparatus for a device under test fixture' [patent_app_type] => new [patent_app_number] => 09/772233 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2999 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20020101255.pdf [firstpage_image] =>[orig_patent_app_number] => 09772233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/772233
Method and apparatus for a device under test fixture Jan 28, 2001 Abandoned
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