Jing-yih Shyu

Array ( [id] => 10786294 [patent_doc_number] => 20160132450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'NETWORK CONTROLLER - SIDEBAND INTERFACE PORT CONTROLLER' [patent_app_type] => utility [patent_app_number] => 14/857999 [patent_app_country] => US [patent_app_date] => 2015-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5203 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14857999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10724520 [patent_doc_number] => 20160070668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'QUASI-OPTIMIZED INTERCONNECTION NETWORK FOR, AND METHOD OF, INTERCONNECTING NODES IN LARGE-SCALE, PARALLEL SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/847200 [patent_app_country] => US [patent_app_date] => 2015-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2833 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14847200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12108227 [patent_doc_number] => 09864712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Shared receive queue allocation for network on a chip communication' [patent_app_type] => utility [patent_app_number] => 14/838073 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10300 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14838073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11257871 [patent_doc_number] => 09482769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'High performance and grid computing with partitioning quality of service control' [patent_app_type] => utility [patent_app_number] => 14/835380 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7594 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10477602 [patent_doc_number] => 20150362619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'HIGH PERFORMANCE AND GRID COMPUTING WITH FAULT TOLERANT DATA DISTRIBUTORS QUALITY OF SERVICE' [patent_app_type] => utility [patent_app_number] => 14/835279 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7491 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12039541 [patent_doc_number] => 09817775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Control system for hard disk' [patent_app_type] => utility [patent_app_number] => 14/809407 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1270 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11903529 [patent_doc_number] => 09772963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Interrupt management system for deferring low priority interrupts in real-time system' [patent_app_type] => utility [patent_app_number] => 14/809269 [patent_app_country] => US [patent_app_date] => 2015-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7204 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12146713 [patent_doc_number] => 09880967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Method and system maintaining quality of service (QoS) of host commands in multi-port, multi-function peripheral component interconnect express (PCIe) devices' [patent_app_type] => utility [patent_app_number] => 14/800750 [patent_app_country] => US [patent_app_date] => 2015-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4087 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13449259 [patent_doc_number] => 20180276172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => CIRCUIT FOR INHIBITING SINGLE-ENDED ANALOGUE SIGNAL NOISE, AND TERMINAL ATTACHMENT [patent_app_type] => utility [patent_app_number] => 15/743540 [patent_app_country] => US [patent_app_date] => 2015-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15743540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12914791 [patent_doc_number] => 20180196773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => METHOD AND HOST NODE FOR CONFIGURING A REMOTE NODE AND A HOST NODE [patent_app_type] => utility [patent_app_number] => 15/743221 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15743221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12914509 [patent_doc_number] => 20180196679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => INITIALIZATION METHOD FOR USE IN I2C SYSTEM AND MASTER DEVICE [patent_app_type] => utility [patent_app_number] => 15/740557 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15740557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13679263 [patent_doc_number] => 20160378368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => PERFORMING PREPROCESSING OPERATIONS IN ANTICIPATION OF LOG FILE WRITES [patent_app_type] => utility [patent_app_number] => 14/751703 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11903357 [patent_doc_number] => 09772792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-26 [patent_title] => 'Coordinated resource allocation between container groups and storage groups' [patent_app_type] => utility [patent_app_number] => 14/752153 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10408863 [patent_doc_number] => 20150293872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'DUAL SERIAL/PARALLEL INTERFACE DEVICES AND SWITCHING COMPONENTS' [patent_app_type] => utility [patent_app_number] => 14/748705 [patent_app_country] => US [patent_app_date] => 2015-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7695 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14748705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10485724 [patent_doc_number] => 20150370742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'FRONT END TRAFFIC HANDLING IN MODULAR SWITCHED FABRIC BASED DATA STORAGE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/747450 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 29973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14747450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10393123 [patent_doc_number] => 20150278130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'COMPLETION NOTIFICATION FOR A STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/739709 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9984 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14739709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11078061 [patent_doc_number] => 20160275025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'PREVENTING SOFTWARE THREAD BLOCKING DUE TO INTERRUPTS' [patent_app_type] => utility [patent_app_number] => 14/737359 [patent_app_country] => US [patent_app_date] => 2015-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7491 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14737359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10393140 [patent_doc_number] => 20150278146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Method And Apparatus For Providing Traffic Re-Aware Slot Placement' [patent_app_type] => utility [patent_app_number] => 14/731980 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8637 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14731980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12046444 [patent_doc_number] => 09824047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Discovery mechanisms for universal serial bus (USB) protocol adaptation layer' [patent_app_type] => utility [patent_app_number] => 14/729399 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5272 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14729399 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10371704 [patent_doc_number] => 20150256709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND DEVICE LINKAGE METHOD' [patent_app_type] => utility [patent_app_number] => 14/718994 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 19183 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718994 [rel_patent_id] =>[rel_patent_doc_number] =>)