Search

Jing-yih Shyu

Examiner (ID: 7802, Phone: (571)270-3488 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184
Total Applications
628
Issued Applications
545
Pending Applications
0
Abandoned Applications
86

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12187577 [patent_doc_number] => 20180046513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'Disaggregated Fabric-Switched Computing Platform' [patent_app_type] => utility [patent_app_number] => 15/675377 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13940 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675377 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675377
Disaggregated fabric-switched computing platform Aug 10, 2017 Issued
Array ( [id] => 16370961 [patent_doc_number] => 10802716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Hard disk management method, system, electronic device, and storage medium [patent_app_type] => utility [patent_app_number] => 16/322201 [patent_app_country] => US [patent_app_date] => 2017-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6179 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16322201 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/322201
Hard disk management method, system, electronic device, and storage medium Jul 25, 2017 Issued
Array ( [id] => 13045379 [patent_doc_number] => 10044837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Generation and distribution of named, definable, serialized tokens [patent_app_type] => utility [patent_app_number] => 15/655926 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8673 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 596 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655926 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/655926
Generation and distribution of named, definable, serialized tokens Jul 20, 2017 Issued
Array ( [id] => 12004304 [patent_doc_number] => 20170308459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'ORTHOGONAL EXPERIMENTATION IN A COMPUTING ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 15/644626 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7883 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/644626
Orthogonal experimentation in a computing environment Jul 6, 2017 Issued
Array ( [id] => 13611287 [patent_doc_number] => 20180357193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => COMPUTING DEVICE AND OPERATION METHOD [patent_app_type] => utility [patent_app_number] => 15/641161 [patent_app_country] => US [patent_app_date] => 2017-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641161 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/641161
COMPUTING DEVICE AND OPERATION METHOD Jul 2, 2017 Abandoned
Array ( [id] => 14255121 [patent_doc_number] => 10277774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Information processing apparatus, information processing system, and device linkage method [patent_app_type] => utility [patent_app_number] => 15/621828 [patent_app_country] => US [patent_app_date] => 2017-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 37 [patent_no_of_words] => 18838 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15621828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/621828
Information processing apparatus, information processing system, and device linkage method Jun 12, 2017 Issued
Array ( [id] => 12033573 [patent_doc_number] => 20170323672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'MEMORY CONTROLLER WITH PHASE ADJUSTED CLOCK FOR PERFORMING MEMORY OPERATIONS' [patent_app_type] => utility [patent_app_number] => 15/604251 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604251 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604251
Memory controller with phase adjusted clock for performing memory operations May 23, 2017 Issued
Array ( [id] => 11846545 [patent_doc_number] => 09734099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-15 [patent_title] => 'QSPI based methods of simultaneously controlling multiple SPI peripherals' [patent_app_type] => utility [patent_app_number] => 15/499640 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6740 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 422 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499640 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499640
QSPI based methods of simultaneously controlling multiple SPI peripherals Apr 26, 2017 Issued
Array ( [id] => 11853114 [patent_doc_number] => 20170227606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'FALLING CLOCK EDGE JTAG BUS ROUTERS' [patent_app_type] => utility [patent_app_number] => 15/499362 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13718 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499362 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499362
TDI, TCK, TMS, TDO, first, second, third, gating routing circuit Apr 26, 2017 Issued
Array ( [id] => 12004333 [patent_doc_number] => 20170308488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'Communication Interface Between Host System and State Machine' [patent_app_type] => utility [patent_app_number] => 15/496127 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496127 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496127
Communications interface circuit architecture Apr 24, 2017 Issued
Array ( [id] => 17091772 [patent_doc_number] => 11119962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Apparatus and method for multiplexing data transport by switching different data protocols through a common bond pad [patent_app_type] => utility [patent_app_number] => 15/496232 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496232 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496232
Apparatus and method for multiplexing data transport by switching different data protocols through a common bond pad Apr 24, 2017 Issued
Array ( [id] => 14175841 [patent_doc_number] => 10261936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => PCIe switch with data and control path systolic array [patent_app_type] => utility [patent_app_number] => 15/494606 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2259 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15494606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/494606
PCIe switch with data and control path systolic array Apr 23, 2017 Issued
Array ( [id] => 13511489 [patent_doc_number] => 20180307287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => MODULE COMMUNICATIONS VIA POWER DELIVERY BUSES [patent_app_type] => utility [patent_app_number] => 15/494629 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15494629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/494629
Module communications via power delivery buses Apr 23, 2017 Issued
Array ( [id] => 12869011 [patent_doc_number] => 20180181512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => SYNCHRONIZATION OF A NETWORK OF SENSORS [patent_app_type] => utility [patent_app_number] => 15/495636 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15495636 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/495636
Synchronization of a network of sensors Apr 23, 2017 Issued
Array ( [id] => 14203459 [patent_doc_number] => 10268847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => System and method for repurposing communication ports as host interface or data card connections [patent_app_type] => utility [patent_app_number] => 15/493863 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10653 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493863
System and method for repurposing communication ports as host interface or data card connections Apr 20, 2017 Issued
Array ( [id] => 11745945 [patent_doc_number] => 20170200017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'Systems And Methods For Managing Authority Designation And Event Handling For Hierarchical Graphical User Interfaces' [patent_app_type] => utility [patent_app_number] => 15/467498 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/467498
Systems and methods for managing authority designation and event handling for hierarchical graphical user interfaces Mar 22, 2017 Issued
Array ( [id] => 12161197 [patent_doc_number] => 20180032463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'SYSTEM ARCHITECTURE FOR SUPPORTING ACTIVE PASS-THROUGH BOARD FOR MULTI-MODE NMVE OVER FABRICS DEVICES' [patent_app_type] => utility [patent_app_number] => 15/459482 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7638 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15459482 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/459482
System architecture for supporting active pass-through board for multi-mode NMVE over fabrics devices Mar 14, 2017 Issued
Array ( [id] => 15839957 [patent_doc_number] => 20200135261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => CONTROL DEVICE, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD FOR A SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/491899 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -34 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16491899 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/491899
Semiconductor memory device comprising an interface conforming to JEDEC standard and control device therefor Mar 5, 2017 Issued
Array ( [id] => 15402335 [patent_doc_number] => 10541835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Method for initializing a bus system with automatic closure after a predefined period of time, and bus system for performing the method [patent_app_type] => utility [patent_app_number] => 16/098666 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5325 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16098666 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/098666
Method for initializing a bus system with automatic closure after a predefined period of time, and bus system for performing the method Feb 1, 2017 Issued
Array ( [id] => 12161203 [patent_doc_number] => 20180032469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'MULTI-MODE NMVE OVER FABRICS DEVICES' [patent_app_type] => utility [patent_app_number] => 15/411962 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8737 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411962 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411962
Multi-mode NMVE over fabrics devices Jan 19, 2017 Issued
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