
John A. Bodnar
Examiner (ID: 16731, Phone: (571)272-4660 , Office: P/2893 )
| Most Active Art Unit | 2893 |
| Art Unit(s) | 2893 |
| Total Applications | 735 |
| Issued Applications | 584 |
| Pending Applications | 85 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18031950
[patent_doc_number] => 11515148
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-29
[patent_title] => Method for producing at least one device in compressive strained semiconductor
[patent_app_type] => utility
[patent_app_number] => 16/914541
[patent_app_country] => US
[patent_app_date] => 2020-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 5599
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914541
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/914541 | Method for producing at least one device in compressive strained semiconductor | Jun 28, 2020 | Issued |
Array
(
[id] => 16586228
[patent_doc_number] => 20210020630
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-21
[patent_title] => HIGH-VOLTAGE TOLERANT SEMICONDUCTOR ELEMENT
[patent_app_type] => utility
[patent_app_number] => 16/901366
[patent_app_country] => US
[patent_app_date] => 2020-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5833
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901366
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/901366 | HIGH-VOLTAGE TOLERANT SEMICONDUCTOR ELEMENT | Jun 14, 2020 | Abandoned |
Array
(
[id] => 16515994
[patent_doc_number] => 20200395252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-17
[patent_title] => Method for Forming a Superjunction Transistor Device
[patent_app_type] => utility
[patent_app_number] => 16/900329
[patent_app_country] => US
[patent_app_date] => 2020-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11543
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900329
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/900329 | Method for forming a superjunction transistor device | Jun 11, 2020 | Issued |
Array
(
[id] => 18113211
[patent_doc_number] => 20230006091
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/781357
[patent_app_country] => US
[patent_app_date] => 2020-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5633
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17781357
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/781357 | Semiconductor structures and methods of manufacturing the same | Jun 10, 2020 | Issued |
Array
(
[id] => 17159115
[patent_doc_number] => 20210320166
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-14
[patent_title] => DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/260659
[patent_app_country] => US
[patent_app_date] => 2020-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14937
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17260659
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/260659 | Display substrate, display panel and display apparatus | Jun 9, 2020 | Issued |
Array
(
[id] => 16332418
[patent_doc_number] => 20200303384
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => NOR FLASH MEMORY AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/893411
[patent_app_country] => US
[patent_app_date] => 2020-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4617
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893411
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/893411 | NOR flash memory and manufacturing method thereof | Jun 3, 2020 | Issued |
Array
(
[id] => 17847900
[patent_doc_number] => 11437285
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-06
[patent_title] => Trench plug hardmask for advanced integrated circuit structure fabrication
[patent_app_type] => utility
[patent_app_number] => 16/881514
[patent_app_country] => US
[patent_app_date] => 2020-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 121
[patent_figures_cnt] => 223
[patent_no_of_words] => 73398
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881514
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/881514 | Trench plug hardmask for advanced integrated circuit structure fabrication | May 21, 2020 | Issued |
Array
(
[id] => 16241651
[patent_doc_number] => 20200258885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => METHOD FOR CONVERTING A FLOATING GATE NON-VOLATILE MEMORY CELL TO A READ-ONLY MEMORY CELL AND CIRCUIT STRUCTURE THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/863856
[patent_app_country] => US
[patent_app_date] => 2020-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7895
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863856
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/863856 | Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof | Apr 29, 2020 | Issued |
Array
(
[id] => 17395845
[patent_doc_number] => 11244869
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-08
[patent_title] => Fabrication of logic devices and power devices on the same substrate
[patent_app_type] => utility
[patent_app_number] => 16/860919
[patent_app_country] => US
[patent_app_date] => 2020-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 8732
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860919
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/860919 | Fabrication of logic devices and power devices on the same substrate | Apr 27, 2020 | Issued |
Array
(
[id] => 16241554
[patent_doc_number] => 20200258788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/859959
[patent_app_country] => US
[patent_app_date] => 2020-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3209
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859959
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/859959 | Semiconductor device and method for fabricating the same | Apr 26, 2020 | Issued |
Array
(
[id] => 16624869
[patent_doc_number] => 20210043522
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-11
[patent_title] => APPARATUS AND METHOD FOR SIMULTANEOUS FORMATION OF DIFFUSION BREAK, GATE CUT, AND INDEPENDENT N AND P GATES FOR 3D TRANSISTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/848638
[patent_app_country] => US
[patent_app_date] => 2020-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5504
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16848638
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/848638 | Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices | Apr 13, 2020 | Issued |
Array
(
[id] => 16210687
[patent_doc_number] => 20200243677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-30
[patent_title] => Three Dimensional Memory
[patent_app_type] => utility
[patent_app_number] => 16/845793
[patent_app_country] => US
[patent_app_date] => 2020-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6540
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845793
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/845793 | Three dimensional memory | Apr 9, 2020 | Issued |
Array
(
[id] => 16223993
[patent_doc_number] => 20200249110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-06
[patent_title] => CAPACITIVE PRESSURE SENSOR
[patent_app_type] => utility
[patent_app_number] => 16/844684
[patent_app_country] => US
[patent_app_date] => 2020-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7319
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844684
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/844684 | Capacitive pressure sensor | Apr 8, 2020 | Issued |
Array
(
[id] => 17196229
[patent_doc_number] => 11164996
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-02
[patent_title] => Semiconductor light-emitting device and method of manufacturing semiconductor light-emitting device
[patent_app_type] => utility
[patent_app_number] => 16/838468
[patent_app_country] => US
[patent_app_date] => 2020-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 6387
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16838468
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/838468 | Semiconductor light-emitting device and method of manufacturing semiconductor light-emitting device | Apr 1, 2020 | Issued |
Array
(
[id] => 16332229
[patent_doc_number] => 20200303195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => METHOD OF SELECTIVELY FORMING METAL SILICIDES FOR SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/823071
[patent_app_country] => US
[patent_app_date] => 2020-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4371
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823071
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/823071 | Method of selectively forming metal silicides for semiconductor devices | Mar 17, 2020 | Issued |
Array
(
[id] => 20130541
[patent_doc_number] => 12372850
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-29
[patent_title] => Electrically tunable quantum information processing device based on a doped semiconductor structure embedded with a defect
[patent_app_type] => utility
[patent_app_number] => 17/438600
[patent_app_country] => US
[patent_app_date] => 2020-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 7012
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17438600
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/438600 | Electrically tunable quantum information processing device based on a doped semiconductor structure embedded with a defect | Mar 12, 2020 | Issued |
Array
(
[id] => 16724074
[patent_doc_number] => 20210091221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/816871
[patent_app_country] => US
[patent_app_date] => 2020-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3774
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16816871
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/816871 | Semiconductor device | Mar 11, 2020 | Issued |
Array
(
[id] => 16099039
[patent_doc_number] => 20200203506
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/807633
[patent_app_country] => US
[patent_app_date] => 2020-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3691
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807633
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/807633 | Semiconductor device and method for manufacturing the same | Mar 2, 2020 | Issued |
Array
(
[id] => 18016428
[patent_doc_number] => 11508735
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-22
[patent_title] => Cell manufacturing
[patent_app_type] => utility
[patent_app_number] => 16/806102
[patent_app_country] => US
[patent_app_date] => 2020-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
[patent_figures_cnt] => 57
[patent_no_of_words] => 16907
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806102
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/806102 | Cell manufacturing | Mar 1, 2020 | Issued |
Array
(
[id] => 17901094
[patent_doc_number] => 20220310756
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/430229
[patent_app_country] => US
[patent_app_date] => 2020-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19121
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17430229
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/430229 | Display substrate and manufacturing method thereof, and display apparatus | Feb 26, 2020 | Issued |