John A. Bodnar

Array ( [id] => 14676889 [patent_doc_number] => 20190237559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => FORMING NANOSHEET TRANSISTOR USING SACRIFICIAL SPACER AND INNER SPACERS [patent_app_type] => utility [patent_app_number] => 15/880757 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13364121 [patent_doc_number] => 20180233600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => WRAP-AROUND GATE STRUCTURES AND METHODS OF FORMING WRAP-AROUND GATE STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/879109 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15185285 [patent_doc_number] => 20190363234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => Optoelectronic Semiconductor Component and Method for Producing an Optoelectronic Semiconductor Component [patent_app_type] => utility [patent_app_number] => 16/476863 [patent_app_country] => US [patent_app_date] => 2018-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13321037 [patent_doc_number] => 20180212056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => STRAINED SEMICONDUCTOR-ON-INSULATOR BY DEFORMATION OF BURIED INSULATOR INDUCED BY BURIED STRESSOR [patent_app_type] => utility [patent_app_number] => 15/877273 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15488447 [patent_doc_number] => 10559585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Vertical memory devices with conductive pads supported by dummy channels with varying dimensions [patent_app_type] => utility [patent_app_number] => 15/871478 [patent_app_country] => US [patent_app_date] => 2018-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6662 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13629999 [patent_doc_number] => 20180366552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/869642 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15869642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14588061 [patent_doc_number] => 20190221639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => NANOSHEET DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/870267 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15315379 [patent_doc_number] => 10522403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Middle of the line self-aligned direct pattern contacts [patent_app_type] => utility [patent_app_number] => 15/868479 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16432868 [patent_doc_number] => 10832965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Fin reveal forming STI regions having convex shape between fins [patent_app_type] => utility [patent_app_number] => 15/868229 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4723 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15061765 [patent_doc_number] => 10461195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/864330 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 9944 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12918085 [patent_doc_number] => 20180197871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => FLASH MEMORY DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/863754 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12917830 [patent_doc_number] => 20180197786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/863581 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16034943 [patent_doc_number] => 10679903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/859775 [patent_app_country] => US [patent_app_date] => 2018-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3180 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16502600 [patent_doc_number] => 10867998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-15 [patent_title] => Semiconductor structure cutting process and structures formed thereby [patent_app_type] => utility [patent_app_number] => 15/860492 [patent_app_country] => US [patent_app_date] => 2018-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 69 [patent_no_of_words] => 10545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15860492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14381857 [patent_doc_number] => 20190164841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => TRENCH PLUG HARDMASK FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 15/859411 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16653560 [patent_doc_number] => 10930753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Trench isolation for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 15/859286 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 73455 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14381793 [patent_doc_number] => 20190164809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => CONTINUOUS GATE AND FIN SPACER FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 15/859323 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13996581 [patent_doc_number] => 20190067448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => GATE STRUCTURE FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/857196 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15401293 [patent_doc_number] => 10541309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Semiconductor structure and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/853867 [patent_app_country] => US [patent_app_date] => 2017-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2306 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15853867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16048007 [patent_doc_number] => 10685886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Fabrication of logic devices and power devices on the same substrate [patent_app_type] => utility [patent_app_number] => 15/843786 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 8732 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843786 [rel_patent_id] =>[rel_patent_doc_number] =>)