Search

John A. Bodnar

Examiner (ID: 2515, Phone: (571)272-4660 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893
Total Applications
777
Issued Applications
614
Pending Applications
81
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17421123 [patent_doc_number] => 11254563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Mold material architecture for package device structures [patent_app_type] => utility [patent_app_number] => 15/962912 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8056 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962912 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/962912
Mold material architecture for package device structures Apr 24, 2018 Issued
Array ( [id] => 13378697 [patent_doc_number] => 20180240890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => METAL OXIDE SEMICONDUCTOR (MOS) ISOLATION SCHEMES WITH CONTINUOUS ACTIVE AREAS SEPARATED BY DUMMY GATES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 15/962023 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/962023
METAL OXIDE SEMICONDUCTOR (MOS) ISOLATION SCHEMES WITH CONTINUOUS ACTIVE AREAS SEPARATED BY DUMMY GATES AND RELATED METHODS Apr 24, 2018 Abandoned
Array ( [id] => 18736944 [patent_doc_number] => 11805700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Laminated substrate having piezoelectric film, element having piezoelectric film and method for manufacturing this laminated substrate [patent_app_type] => utility [patent_app_number] => 16/619871 [patent_app_country] => US [patent_app_date] => 2018-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6465 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16619871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/619871
Laminated substrate having piezoelectric film, element having piezoelectric film and method for manufacturing this laminated substrate Apr 18, 2018 Issued
Array ( [id] => 15807699 [patent_doc_number] => 20200126992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/605548 [patent_app_country] => US [patent_app_date] => 2018-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 69264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605548 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/605548
Semiconductor device and manufacturing method of semiconductor device Apr 18, 2018 Issued
Array ( [id] => 15030583 [patent_doc_number] => 20190326296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => THIN-FILM TRANSISTOR EMBEDDED DYNAMIC RANDOM-ACCESS MEMORY WITH SHALLOW BITLINE [patent_app_type] => utility [patent_app_number] => 15/956379 [patent_app_country] => US [patent_app_date] => 2018-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15956379 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/956379
Thin-film transistor embedded dynamic random-access memory with shallow bitline Apr 17, 2018 Issued
Array ( [id] => 19169944 [patent_doc_number] => 11985870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/042877 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17042877 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/042877
Display device Mar 29, 2018 Issued
Array ( [id] => 14938893 [patent_doc_number] => 20190305085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => ASYMMETRICAL SEMICONDUCTOR NANOWIRE FIELD-EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/942252 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942252 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942252
Asymmetrical semiconductor nanowire field-effect transistor Mar 29, 2018 Issued
Array ( [id] => 15840627 [patent_doc_number] => 20200135596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => COVER GLASS AND AIRTIGHT PACKAGE USING SAME [patent_app_type] => utility [patent_app_number] => 16/605629 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605629 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/605629
COVER GLASS AND AIRTIGHT PACKAGE USING SAME Mar 14, 2018 Abandoned
Array ( [id] => 15922231 [patent_doc_number] => 10658364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof [patent_app_type] => utility [patent_app_number] => 15/908575 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 7897 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15908575 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/908575
Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof Feb 27, 2018 Issued
Array ( [id] => 17002773 [patent_doc_number] => 11081596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Semiconductor device and manufacturing device of the same [patent_app_type] => utility [patent_app_number] => 15/904601 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 42 [patent_no_of_words] => 17788 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904601 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/904601
Semiconductor device and manufacturing device of the same Feb 25, 2018 Issued
Array ( [id] => 13936167 [patent_doc_number] => 20190051599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/902806 [patent_app_country] => US [patent_app_date] => 2018-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15902806 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/902806
Semiconductor device and method of manufacturing the same Feb 21, 2018 Issued
Array ( [id] => 13499839 [patent_doc_number] => 20180301462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/900664 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900664 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900664
Semiconductor device and manufacturing method thereof Feb 19, 2018 Issued
Array ( [id] => 14285557 [patent_doc_number] => 20190140063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => SEMICONDUCTOR STRUCTURE FOR MEMORY DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/895378 [patent_app_country] => US [patent_app_date] => 2018-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15895378 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/895378
Semiconductor structure for memory device and method for forming the same Feb 12, 2018 Issued
Array ( [id] => 13613841 [patent_doc_number] => 20180358470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => NONVOLATILE MEMORY DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL AND APPARATUS INCLUDING THE NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/892850 [patent_app_country] => US [patent_app_date] => 2018-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15892850 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/892850
Nonvolatile memory device including two-dimensional material and apparatus including the nonvolatile memory device Feb 8, 2018 Issued
Array ( [id] => 16386580 [patent_doc_number] => 10811425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => NOR flash memory and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/892350 [patent_app_country] => US [patent_app_date] => 2018-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 4593 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15892350 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/892350
NOR flash memory and manufacturing method thereof Feb 7, 2018 Issued
Array ( [id] => 16553197 [patent_doc_number] => 10886364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Vertical memory cell with mechanical structural reinforcement [patent_app_type] => utility [patent_app_number] => 15/889514 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 26 [patent_no_of_words] => 5454 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889514 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/889514
Vertical memory cell with mechanical structural reinforcement Feb 5, 2018 Issued
Array ( [id] => 14382521 [patent_doc_number] => 20190165173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => Gate Structure and Method with Enhanced Gate Contact and Threshold Voltage [patent_app_type] => utility [patent_app_number] => 15/884614 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/884614
Gate structure and method with enhanced gate contact and threshold voltage Jan 30, 2018 Issued
Array ( [id] => 14676889 [patent_doc_number] => 20190237559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => FORMING NANOSHEET TRANSISTOR USING SACRIFICIAL SPACER AND INNER SPACERS [patent_app_type] => utility [patent_app_number] => 15/880757 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880757 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880757
Forming nanosheet transistor using sacrificial spacer and inner spacers Jan 25, 2018 Issued
Array ( [id] => 13364121 [patent_doc_number] => 20180233600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => WRAP-AROUND GATE STRUCTURES AND METHODS OF FORMING WRAP-AROUND GATE STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/879109 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879109
Wrap-around gate structures and methods of forming wrap-around gate structures Jan 23, 2018 Issued
Array ( [id] => 15185285 [patent_doc_number] => 20190363234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => Optoelectronic Semiconductor Component and Method for Producing an Optoelectronic Semiconductor Component [patent_app_type] => utility [patent_app_number] => 16/476863 [patent_app_country] => US [patent_app_date] => 2018-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476863 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/476863
Optoelectronic semiconductor component and method for producing an optoelectronic semiconductor component Jan 22, 2018 Issued
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