
John A. Bodnar
Examiner (ID: 584, Phone: (571)272-4660 , Office: P/2893 )
| Most Active Art Unit | 2893 |
| Art Unit(s) | 2893 |
| Total Applications | 740 |
| Issued Applications | 594 |
| Pending Applications | 69 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14050075
[patent_doc_number] => 20190081145
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-14
[patent_title] => CONTACT TO SOURCE/DRAIN REGIONS AND METHOD OF FORMING SAME
[patent_app_type] => utility
[patent_app_number] => 15/701678
[patent_app_country] => US
[patent_app_date] => 2017-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12343
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701678
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/701678 | CONTACT TO SOURCE/DRAIN REGIONS AND METHOD OF FORMING SAME | Sep 11, 2017 | Abandoned |
Array
(
[id] => 13950867
[patent_doc_number] => 10211212
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-19
[patent_title] => Semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 15/701527
[patent_app_country] => US
[patent_app_date] => 2017-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 40
[patent_no_of_words] => 9651
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701527
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/701527 | Semiconductor devices | Sep 11, 2017 | Issued |
Array
(
[id] => 13420145
[patent_doc_number] => 20180261615
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-13
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/700408
[patent_app_country] => US
[patent_app_date] => 2017-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7473
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700408
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/700408 | SEMICONDUCTOR MEMORY DEVICE | Sep 10, 2017 | Abandoned |
Array
(
[id] => 13909049
[patent_doc_number] => 20190043729
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-07
[patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/698765
[patent_app_country] => US
[patent_app_date] => 2017-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5256
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698765
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/698765 | Semiconductor device structure and manufacturing method thereof | Sep 7, 2017 | Issued |
Array
(
[id] => 14301007
[patent_doc_number] => 10290635
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-14
[patent_title] => Buried interconnect conductor
[patent_app_type] => utility
[patent_app_number] => 15/698030
[patent_app_country] => US
[patent_app_date] => 2017-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 33
[patent_no_of_words] => 7568
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698030
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/698030 | Buried interconnect conductor | Sep 6, 2017 | Issued |
Array
(
[id] => 13098929
[patent_doc_number] => 10068810
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-09-04
[patent_title] => Multiple Fin heights with dielectric isolation
[patent_app_type] => utility
[patent_app_number] => 15/697661
[patent_app_country] => US
[patent_app_date] => 2017-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 15
[patent_no_of_words] => 4527
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15697661
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/697661 | Multiple Fin heights with dielectric isolation | Sep 6, 2017 | Issued |
Array
(
[id] => 13862477
[patent_doc_number] => 10192966
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => Semiconductor devices including recessed gate electrode portions
[patent_app_type] => utility
[patent_app_number] => 15/692560
[patent_app_country] => US
[patent_app_date] => 2017-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 41
[patent_no_of_words] => 6707
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692560
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/692560 | Semiconductor devices including recessed gate electrode portions | Aug 30, 2017 | Issued |
Array
(
[id] => 15286619
[patent_doc_number] => 10515979
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-24
[patent_title] => Three-dimensional semiconductor devices with inclined gate electrodes
[patent_app_type] => utility
[patent_app_number] => 15/692281
[patent_app_country] => US
[patent_app_date] => 2017-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 12369
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692281
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/692281 | Three-dimensional semiconductor devices with inclined gate electrodes | Aug 30, 2017 | Issued |
Array
(
[id] => 16132391
[patent_doc_number] => 10699963
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-30
[patent_title] => Structure and formation method of semiconductor device structure with isolation feature
[patent_app_type] => utility
[patent_app_number] => 15/692072
[patent_app_country] => US
[patent_app_date] => 2017-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8168
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692072
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/692072 | Structure and formation method of semiconductor device structure with isolation feature | Aug 30, 2017 | Issued |
Array
(
[id] => 15061625
[patent_doc_number] => 10461125
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-29
[patent_title] => Three dimensional memory arrays
[patent_app_type] => utility
[patent_app_number] => 15/689155
[patent_app_country] => US
[patent_app_date] => 2017-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6130
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689155
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/689155 | Three dimensional memory arrays | Aug 28, 2017 | Issued |
Array
(
[id] => 13996519
[patent_doc_number] => 20190067417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-28
[patent_title] => Fill Fins for Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 15/689466
[patent_app_country] => US
[patent_app_date] => 2017-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9160
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689466
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/689466 | Fill fins for semiconductor devices | Aug 28, 2017 | Issued |
Array
(
[id] => 13996237
[patent_doc_number] => 20190067276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-28
[patent_title] => FINFET ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/686860
[patent_app_country] => US
[patent_app_date] => 2017-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8486
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686860
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/686860 | FinFET isolation structure and method for fabricating the same | Aug 24, 2017 | Issued |
Array
(
[id] => 13996297
[patent_doc_number] => 20190067306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-28
[patent_title] => SEMICONDUCTOR DEVICE STRUCTURES COMPRISING CARBON-DOPED SILICON NITRIDE AND RELATED METHODS
[patent_app_type] => utility
[patent_app_number] => 15/685690
[patent_app_country] => US
[patent_app_date] => 2017-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6279
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15685690
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/685690 | Semiconductor devices comprising carbon-doped silicon nitride and related methods | Aug 23, 2017 | Issued |
Array
(
[id] => 13667745
[patent_doc_number] => 10164054
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-25
[patent_title] => Compound semiconductor field effect transistor with self-aligned gate
[patent_app_type] => utility
[patent_app_number] => 15/683530
[patent_app_country] => US
[patent_app_date] => 2017-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 50
[patent_no_of_words] => 15219
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683530
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/683530 | Compound semiconductor field effect transistor with self-aligned gate | Aug 21, 2017 | Issued |
Array
(
[id] => 12218991
[patent_doc_number] => 20180057350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-01
[patent_title] => 'MICROMECHANICAL SYSTEM HAVING A STOP ELEMENT'
[patent_app_type] => utility
[patent_app_number] => 15/681062
[patent_app_country] => US
[patent_app_date] => 2017-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3039
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681062
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/681062 | MICROMECHANICAL SYSTEM HAVING A STOP ELEMENT | Aug 17, 2017 | Abandoned |
Array
(
[id] => 16027877
[patent_doc_number] => 10676345
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-09
[patent_title] => Temperature stabilized MEMS device
[patent_app_type] => utility
[patent_app_number] => 15/677057
[patent_app_country] => US
[patent_app_date] => 2017-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3001
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677057
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/677057 | Temperature stabilized MEMS device | Aug 14, 2017 | Issued |
Array
(
[id] => 13963377
[patent_doc_number] => 20190058033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-21
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/677089
[patent_app_country] => US
[patent_app_date] => 2017-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4550
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677089
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/677089 | Semiconductor device and manufacturing method thereof | Aug 14, 2017 | Issued |
Array
(
[id] => 12061962
[patent_doc_number] => 20170338306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'Method for Manufacturing a Power Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 15/669537
[patent_app_country] => US
[patent_app_date] => 2017-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7635
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669537
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/669537 | Method for manufacturing a power semiconductor device | Aug 3, 2017 | Issued |
Array
(
[id] => 13901357
[patent_doc_number] => 20190039883
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-07
[patent_title] => MONOLITHIC PHASE CHANGE HEAT SINK
[patent_app_type] => utility
[patent_app_number] => 15/666475
[patent_app_country] => US
[patent_app_date] => 2017-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5865
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15666475
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/666475 | Monolithic phase change heat sink | Jul 31, 2017 | Issued |
Array
(
[id] => 16245929
[patent_doc_number] => 10745268
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-18
[patent_title] => Method of stiction prevention by patterned anti-stiction layer
[patent_app_type] => utility
[patent_app_number] => 15/665517
[patent_app_country] => US
[patent_app_date] => 2017-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 21
[patent_no_of_words] => 5404
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15665517
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/665517 | Method of stiction prevention by patterned anti-stiction layer | Jul 31, 2017 | Issued |