Search

John A. Bodnar

Examiner (ID: 2515, Phone: (571)272-4660 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893
Total Applications
777
Issued Applications
614
Pending Applications
81
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14603555 [patent_doc_number] => 10354974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Structure and formation method of chip package structure [patent_app_type] => utility [patent_app_number] => 14/736684 [patent_app_country] => US [patent_app_date] => 2015-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3532 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14736684 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/736684
Structure and formation method of chip package structure Jun 10, 2015 Issued
Array ( [id] => 11043823 [patent_doc_number] => 20160240779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'MULTILAYER-STACKED RESISTIVE RANDOM ACCESS MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/736958 [patent_app_country] => US [patent_app_date] => 2015-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2306 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14736958 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/736958
Multilayer-stacked resistive random access memory device Jun 10, 2015 Issued
Array ( [id] => 10472385 [patent_doc_number] => 20150357401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'MULTILAYER ELECTRICAL DEVICE' [patent_app_type] => utility [patent_app_number] => 14/735584 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5670 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735584 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735584
Multilayer electrical device Jun 9, 2015 Issued
Array ( [id] => 11539723 [patent_doc_number] => 09614143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'De-integrated trench formation for advanced MRAM integration' [patent_app_type] => utility [patent_app_number] => 14/735006 [patent_app_country] => US [patent_app_date] => 2015-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10625 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735006 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735006
De-integrated trench formation for advanced MRAM integration Jun 8, 2015 Issued
Array ( [id] => 11551604 [patent_doc_number] => 09620461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Laminar structure of semiconductor and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/734779 [patent_app_country] => US [patent_app_date] => 2015-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3423 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14734779 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/734779
Laminar structure of semiconductor and manufacturing method thereof Jun 8, 2015 Issued
Array ( [id] => 11250201 [patent_doc_number] => 09475693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'ASIC element, in particular as a component of a vertically integrated hybrid component' [patent_app_type] => utility [patent_app_number] => 14/732998 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1772 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732998 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732998
ASIC element, in particular as a component of a vertically integrated hybrid component Jun 7, 2015 Issued
Array ( [id] => 11328342 [patent_doc_number] => 20160358954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'DEEP TRENCH SIDEWALL ETCH STOP' [patent_app_type] => utility [patent_app_number] => 14/733156 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14733156 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/733156
Deep trench sidewall etch stop Jun 7, 2015 Issued
Array ( [id] => 11466925 [patent_doc_number] => 09583565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Semiconductor device with isolating layer on side and bottom surfaces' [patent_app_type] => utility [patent_app_number] => 14/731970 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8810 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14731970 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/731970
Semiconductor device with isolating layer on side and bottom surfaces Jun 4, 2015 Issued
Array ( [id] => 10472576 [patent_doc_number] => 20150357593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/732381 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3154 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732381 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732381
ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE Jun 4, 2015 Abandoned
Array ( [id] => 10468330 [patent_doc_number] => 20150353345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'Vertical Hybrid Integrated MEMS ASIC Component Having A Stress Decoupling Structure' [patent_app_type] => utility [patent_app_number] => 14/731695 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3071 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14731695 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/731695
Vertical Hybrid Integrated MEMS ASIC Component Having A Stress Decoupling Structure Jun 4, 2015 Abandoned
Array ( [id] => 11184610 [patent_doc_number] => 09416000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-16 [patent_title] => 'Component including two semiconductor elements, between which at least two hermetically sealed cavities are formed and method for establishing a corresponding bonding connection between two semiconductor elements' [patent_app_type] => utility [patent_app_number] => 14/731666 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2063 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14731666 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/731666
Component including two semiconductor elements, between which at least two hermetically sealed cavities are formed and method for establishing a corresponding bonding connection between two semiconductor elements Jun 4, 2015 Issued
Array ( [id] => 11615752 [patent_doc_number] => 09653617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Multiple junction thin film transistor' [patent_app_type] => utility [patent_app_number] => 14/723038 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 42 [patent_no_of_words] => 22582 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723038 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723038
Multiple junction thin film transistor May 26, 2015 Issued
Array ( [id] => 13257619 [patent_doc_number] => 10141507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Biased plasma oxidation method for rounding structure [patent_app_type] => utility [patent_app_number] => 14/723315 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3462 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723315 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723315
Biased plasma oxidation method for rounding structure May 26, 2015 Issued
Array ( [id] => 11293786 [patent_doc_number] => 20160343719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'INTERPOSERS FOR INTEGRATED CIRCUITS WITH ONE-TIME PROGRAMMING AND METHODS FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/719499 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14719499 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/719499
INTERPOSERS FOR INTEGRATED CIRCUITS WITH ONE-TIME PROGRAMMING AND METHODS FOR MANUFACTURING THE SAME May 21, 2015 Abandoned
Array ( [id] => 11293676 [patent_doc_number] => 20160343608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY' [patent_app_type] => utility [patent_app_number] => 14/718769 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 6002 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718769 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/718769
Shallow trench isolation trenches and methods for NAND memory May 20, 2015 Issued
Array ( [id] => 10826202 [patent_doc_number] => 20160172371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/712629 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14712629 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/712629
Semiconductor device and method of manufacturing the same May 13, 2015 Issued
Array ( [id] => 11273625 [patent_doc_number] => 20160336172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'LITHOGRAPHY STACK AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/712197 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14712197 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/712197
LITHOGRAPHY STACK AND METHOD May 13, 2015 Abandoned
Array ( [id] => 11096757 [patent_doc_number] => 20160293726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'PATTERNED STRUCTURE OF A SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/710602 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4099 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14710602 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/710602
Patterned structure of a semiconductor device and a manufacturing method thereof May 12, 2015 Issued
Array ( [id] => 10351050 [patent_doc_number] => 20150236054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/700562 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22691 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700562 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/700562
Display device Apr 29, 2015 Issued
Array ( [id] => 10343761 [patent_doc_number] => 20150228767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/693551 [patent_app_country] => US [patent_app_date] => 2015-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3809 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14693551 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/693551
Semiconductor memory device and method of manufacturing the same Apr 21, 2015 Issued
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