Search

John A. Bodnar

Examiner (ID: 2515, Phone: (571)272-4660 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893
Total Applications
777
Issued Applications
614
Pending Applications
81
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9984145 [patent_doc_number] => 09029862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Low resistance embedded strap for a trench capacitor' [patent_app_type] => utility [patent_app_number] => 13/901802 [patent_app_country] => US [patent_app_date] => 2013-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7940 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13901802 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/901802
Low resistance embedded strap for a trench capacitor May 23, 2013 Issued
Array ( [id] => 10086286 [patent_doc_number] => 09123640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-01 [patent_title] => 'Three dimensional resistive memory' [patent_app_type] => utility [patent_app_number] => 13/892675 [patent_app_country] => US [patent_app_date] => 2013-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3534 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13892675 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/892675
Three dimensional resistive memory May 12, 2013 Issued
Array ( [id] => 10889416 [patent_doc_number] => 08913418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Confined defect profiling within resistive random memory access cells' [patent_app_type] => utility [patent_app_number] => 13/891472 [patent_app_country] => US [patent_app_date] => 2013-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 11748 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891472 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/891472
Confined defect profiling within resistive random memory access cells May 9, 2013 Issued
Array ( [id] => 9977413 [patent_doc_number] => 09023723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Method of fabricating a gate-all-around word line for a vertical channel DRAM' [patent_app_type] => utility [patent_app_number] => 13/986515 [patent_app_country] => US [patent_app_date] => 2013-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 8245 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 485 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13986515 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/986515
Method of fabricating a gate-all-around word line for a vertical channel DRAM May 8, 2013 Issued
Array ( [id] => 9174538 [patent_doc_number] => 20130316523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/889507 [patent_app_country] => US [patent_app_date] => 2013-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5252 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13889507 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/889507
Method of manufacturing a semiconductor device May 7, 2013 Issued
Array ( [id] => 9972647 [patent_doc_number] => 09019671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Electronic device comprising RF-LDMOS transistor having improved ruggedness' [patent_app_type] => utility [patent_app_number] => 13/887212 [patent_app_country] => US [patent_app_date] => 2013-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5850 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13887212 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/887212
Electronic device comprising RF-LDMOS transistor having improved ruggedness May 2, 2013 Issued
Array ( [id] => 10617967 [patent_doc_number] => 09337421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Multi-layered phase-change memory device' [patent_app_type] => utility [patent_app_number] => 13/874411 [patent_app_country] => US [patent_app_date] => 2013-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 18660 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13874411 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/874411
Multi-layered phase-change memory device Apr 29, 2013 Issued
Array ( [id] => 10919865 [patent_doc_number] => 20140322884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'Nonvolatile resistive memory element with a silicon-based switching layer' [patent_app_type] => utility [patent_app_number] => 13/869800 [patent_app_country] => US [patent_app_date] => 2013-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13869800 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/869800
Nonvolatile resistive memory element with a silicon-based switching layer Apr 23, 2013 Issued
Array ( [id] => 10916578 [patent_doc_number] => 20140319598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS)' [patent_app_type] => utility [patent_app_number] => 13/869869 [patent_app_country] => US [patent_app_date] => 2013-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4930 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13869869 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/869869
Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) Apr 23, 2013 Issued
Array ( [id] => 9038343 [patent_doc_number] => 20130240981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'TRANSISTOR ARRAY WITH A MOSFET AND MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 13/867215 [patent_app_country] => US [patent_app_date] => 2013-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9029 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13867215 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/867215
TRANSISTOR ARRAY WITH A MOSFET AND MANUFACTURING METHOD Apr 21, 2013 Abandoned
Array ( [id] => 9823464 [patent_doc_number] => 08932948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Memory cell floating gate replacement' [patent_app_type] => utility [patent_app_number] => 13/865865 [patent_app_country] => US [patent_app_date] => 2013-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4388 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13865865 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/865865
Memory cell floating gate replacement Apr 17, 2013 Issued
Array ( [id] => 10189648 [patent_doc_number] => 09219078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs' [patent_app_type] => utility [patent_app_number] => 13/865795 [patent_app_country] => US [patent_app_date] => 2013-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5921 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13865795 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/865795
Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs Apr 17, 2013 Issued
Array ( [id] => 10905796 [patent_doc_number] => 20140308808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'Replacement Gate Integration Scheme Employing Multiple Types of Disposable Gate Structures' [patent_app_type] => utility [patent_app_number] => 13/859802 [patent_app_country] => US [patent_app_date] => 2013-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859802 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/859802
Replacement gate integration scheme employing multiple types of disposable gate structures Apr 9, 2013 Issued
Array ( [id] => 9202252 [patent_doc_number] => 20140001429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'HETEROJUNCTION OXIDE MEMORY DEVICE WITH BARRIER LAYER' [patent_app_type] => utility [patent_app_number] => 13/841147 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13841147 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/841147
HETEROJUNCTION OXIDE MEMORY DEVICE WITH BARRIER LAYER Mar 14, 2013 Abandoned
Array ( [id] => 9728905 [patent_doc_number] => 20140264612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'GROWTH OF EPITAXIAL SEMICONDUCTOR REGIONS WITH CURVED TOP SURFACES' [patent_app_type] => utility [patent_app_number] => 13/834514 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13834514 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/834514
GROWTH OF EPITAXIAL SEMICONDUCTOR REGIONS WITH CURVED TOP SURFACES Mar 14, 2013 Abandoned
Array ( [id] => 9515292 [patent_doc_number] => 20140151784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/830912 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8146 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13830912 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/830912
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Mar 13, 2013 Abandoned
Array ( [id] => 9334996 [patent_doc_number] => 20140061778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/800821 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12023 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13800821 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/800821
Semiconductor device having buried bit lines and method for fabricating the same Mar 12, 2013 Issued
Array ( [id] => 9728903 [patent_doc_number] => 20140264610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METAL OXIDE SEMICONDUCTOR (MOS) ISOLATION SCHEMES WITH CONTINUOUS ACTIVE AREAS SEPARATED BY DUMMY GATES AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 13/799955 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5587 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13799955 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/799955
Metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates and related methods Mar 12, 2013 Issued
Array ( [id] => 10617740 [patent_doc_number] => 09337190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Semiconductor device including dummy isolation gate structure and method of fabricating thereof' [patent_app_type] => utility [patent_app_number] => 13/797928 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7141 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13797928 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/797928
Semiconductor device including dummy isolation gate structure and method of fabricating thereof Mar 11, 2013 Issued
Array ( [id] => 9883182 [patent_doc_number] => 08969949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Structure and method for static random access memory device of vertical tunneling field effect transistor' [patent_app_type] => utility [patent_app_number] => 13/792152 [patent_app_country] => US [patent_app_date] => 2013-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6488 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792152 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792152
Structure and method for static random access memory device of vertical tunneling field effect transistor Mar 9, 2013 Issued
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