John A. Bodnar

Array ( [id] => 10876867 [patent_doc_number] => 08901657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-02 [patent_title] => 'Integrated capacitor having an overhanging top capacitor plate' [patent_app_type] => utility [patent_app_number] => 12/541766 [patent_app_country] => US [patent_app_date] => 2009-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3247 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12541766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6285996 [patent_doc_number] => 20100237385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/740310 [patent_app_country] => US [patent_app_date] => 2009-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4003 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237385.pdf [firstpage_image] =>[orig_patent_app_number] => 12740310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6552237 [patent_doc_number] => 20100288756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'COOKER' [patent_app_type] => utility [patent_app_number] => 12/747757 [patent_app_country] => US [patent_app_date] => 2008-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13867 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20100288756.pdf [firstpage_image] =>[orig_patent_app_number] => 12747757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4870673 [patent_doc_number] => 20080197407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Power Semiconductor Devices with Barrier Layer to Reduce Substrate Up-Diffusion and Methods of Manufacture' [patent_app_type] => utility [patent_app_number] => 12/039011 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 73 [patent_no_of_words] => 30535 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197407.pdf [firstpage_image] =>[orig_patent_app_number] => 12039011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7304962 [patent_doc_number] => 20040140556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Integrated chip package structure using silicon substrate and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/755042 [patent_app_country] => US [patent_app_date] => 2004-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6644 [patent_no_of_claims] => 138 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20040140556.pdf [firstpage_image] =>[orig_patent_app_number] => 10755042 [rel_patent_id] =>[rel_patent_doc_number] =>)