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John A. Bodnar

Examiner (ID: 2515, Phone: (571)272-4660 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893
Total Applications
777
Issued Applications
614
Pending Applications
81
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4870673 [patent_doc_number] => 20080197407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Power Semiconductor Devices with Barrier Layer to Reduce Substrate Up-Diffusion and Methods of Manufacture' [patent_app_type] => utility [patent_app_number] => 12/039011 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 73 [patent_no_of_words] => 30535 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197407.pdf [firstpage_image] =>[orig_patent_app_number] => 12039011 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/039011
Power Semiconductor Devices with Barrier Layer to Reduce Substrate Up-Diffusion and Methods of Manufacture Feb 27, 2008 Abandoned
Array ( [id] => 7304962 [patent_doc_number] => 20040140556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Integrated chip package structure using silicon substrate and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/755042 [patent_app_country] => US [patent_app_date] => 2004-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6644 [patent_no_of_claims] => 138 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20040140556.pdf [firstpage_image] =>[orig_patent_app_number] => 10755042 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/755042
Integrated chip package structure using silicon substrate and method of manufacturing the same Jan 8, 2004 Issued
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