Search

John A. Follansbee

Examiner (ID: 19200)

Most Active Art Unit
2783
Art Unit(s)
2444, 2712, 2127, 2154, 2100, 2783, 2302, 2156, 2126, 2451
Total Applications
604
Issued Applications
383
Pending Applications
88
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4194684 [patent_doc_number] => 06085272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Transmitting command block data using the lower address part of the address phase' [patent_app_type] => 1 [patent_app_number] => 9/039302 [patent_app_country] => US [patent_app_date] => 1998-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085272.pdf [firstpage_image] =>[orig_patent_app_number] => 039302 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/039302
Transmitting command block data using the lower address part of the address phase Mar 13, 1998 Issued
Array ( [id] => 4116293 [patent_doc_number] => 06067614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Integrated RISC processor and GPS receiver' [patent_app_type] => 1 [patent_app_number] => 9/026516 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 5843 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067614.pdf [firstpage_image] =>[orig_patent_app_number] => 026516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026516
Integrated RISC processor and GPS receiver Feb 19, 1998 Issued
Array ( [id] => 4312395 [patent_doc_number] => 06237079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Coprocessor interface having pending instructions queue and clean-up queue and dynamically allocating memory' [patent_app_type] => 1 [patent_app_number] => 9/025758 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 135 [patent_figures_cnt] => 167 [patent_no_of_words] => 86163 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237079.pdf [firstpage_image] =>[orig_patent_app_number] => 025758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025758
Coprocessor interface having pending instructions queue and clean-up queue and dynamically allocating memory Feb 17, 1998 Issued
Array ( [id] => 4199365 [patent_doc_number] => 06038662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Bubble evaporation circuit for eliminating bubble errors in thermal code and its method' [patent_app_type] => 1 [patent_app_number] => 9/022859 [patent_app_country] => US [patent_app_date] => 1998-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2627 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038662.pdf [firstpage_image] =>[orig_patent_app_number] => 022859 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022859
Bubble evaporation circuit for eliminating bubble errors in thermal code and its method Feb 11, 1998 Issued
09/021933 EMBEDDED-DRAM-DSP ARCHITECTURE Feb 10, 1998 Abandoned
Array ( [id] => 4256511 [patent_doc_number] => 06081844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Point-to-point interconnect communications utility' [patent_app_type] => 1 [patent_app_number] => 9/013484 [patent_app_country] => US [patent_app_date] => 1998-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 9374 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081844.pdf [firstpage_image] =>[orig_patent_app_number] => 013484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/013484
Point-to-point interconnect communications utility Jan 25, 1998 Issued
Array ( [id] => 4206860 [patent_doc_number] => 06131155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Programmer-visible uncached load/store unit having burst capability' [patent_app_type] => 1 [patent_app_number] => 9/012568 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6052 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131155.pdf [firstpage_image] =>[orig_patent_app_number] => 012568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012568
Programmer-visible uncached load/store unit having burst capability Jan 22, 1998 Issued
Array ( [id] => 3973757 [patent_doc_number] => 05978910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Performing pending interrupts or exceptions when interruptible jumps are detected' [patent_app_type] => 1 [patent_app_number] => 9/009751 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3050 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978910.pdf [firstpage_image] =>[orig_patent_app_number] => 009751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009751
Performing pending interrupts or exceptions when interruptible jumps are detected Jan 19, 1998 Issued
Array ( [id] => 4199379 [patent_doc_number] => 06038663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'IBM PC compatible multi-chip module' [patent_app_type] => 1 [patent_app_number] => 9/008553 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11812 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038663.pdf [firstpage_image] =>[orig_patent_app_number] => 008553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008553
IBM PC compatible multi-chip module Jan 15, 1998 Issued
Array ( [id] => 4381566 [patent_doc_number] => 06256729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method and apparatus for resolving multiple branches' [patent_app_type] => 1 [patent_app_number] => 9/004971 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256729.pdf [firstpage_image] =>[orig_patent_app_number] => 004971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004971
Method and apparatus for resolving multiple branches Jan 8, 1998 Issued
Array ( [id] => 4260852 [patent_doc_number] => 06167529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Instruction dependent clock scheme' [patent_app_type] => 1 [patent_app_number] => 9/001082 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3312 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167529.pdf [firstpage_image] =>[orig_patent_app_number] => 001082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001082
Instruction dependent clock scheme Dec 29, 1997 Issued
Array ( [id] => 4309412 [patent_doc_number] => 06212558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method and apparatus for configuring and managing firewalls and security devices' [patent_app_type] => 1 [patent_app_number] => 8/998100 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 5233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212558.pdf [firstpage_image] =>[orig_patent_app_number] => 998100 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998100
Method and apparatus for configuring and managing firewalls and security devices Dec 23, 1997 Issued
Array ( [id] => 4240278 [patent_doc_number] => 06012138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Dynamically variable length CPU pipeline for efficiently executing two instruction sets' [patent_app_type] => 1 [patent_app_number] => 8/994139 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3378 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012138.pdf [firstpage_image] =>[orig_patent_app_number] => 994139 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994139
Dynamically variable length CPU pipeline for efficiently executing two instruction sets Dec 18, 1997 Issued
Array ( [id] => 4209553 [patent_doc_number] => 06154857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Microprocessor-based device incorporating a cache for capturing software performance profiling data' [patent_app_type] => 1 [patent_app_number] => 8/992610 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 8931 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154857.pdf [firstpage_image] =>[orig_patent_app_number] => 992610 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992610
Microprocessor-based device incorporating a cache for capturing software performance profiling data Dec 16, 1997 Issued
Array ( [id] => 4153463 [patent_doc_number] => 06061309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method and apparatus for maintaining states of an operator panel and convenience input/output station of a dual library manager/dual accessor controller system in the event of a failure to one controller' [patent_app_type] => 1 [patent_app_number] => 8/991902 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4205 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061309.pdf [firstpage_image] =>[orig_patent_app_number] => 991902 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991902
Method and apparatus for maintaining states of an operator panel and convenience input/output station of a dual library manager/dual accessor controller system in the event of a failure to one controller Dec 16, 1997 Issued
Array ( [id] => 4252587 [patent_doc_number] => 06076152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem' [patent_app_type] => 1 [patent_app_number] => 8/992763 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3406 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076152.pdf [firstpage_image] =>[orig_patent_app_number] => 992763 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992763
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem Dec 16, 1997 Issued
Array ( [id] => 4211551 [patent_doc_number] => 06044448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Processor having multiple datapath instances' [patent_app_type] => 1 [patent_app_number] => 8/991392 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4618 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044448.pdf [firstpage_image] =>[orig_patent_app_number] => 991392 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991392
Processor having multiple datapath instances Dec 15, 1997 Issued
Array ( [id] => 4346678 [patent_doc_number] => 06330665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Video parser' [patent_app_type] => 1 [patent_app_number] => 8/992859 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 124 [patent_figures_cnt] => 188 [patent_no_of_words] => 53151 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330665.pdf [firstpage_image] =>[orig_patent_app_number] => 992859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992859
Video parser Dec 9, 1997 Issued
Array ( [id] => 4101058 [patent_doc_number] => 06018797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Integrated relay ladder language, reduced instruction set computer' [patent_app_type] => 1 [patent_app_number] => 8/987033 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5666 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018797.pdf [firstpage_image] =>[orig_patent_app_number] => 987033 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987033
Integrated relay ladder language, reduced instruction set computer Dec 8, 1997 Issued
Array ( [id] => 4162611 [patent_doc_number] => 06032250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method and apparatus for identifying instruction boundaries' [patent_app_type] => 1 [patent_app_number] => 8/986008 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4105 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032250.pdf [firstpage_image] =>[orig_patent_app_number] => 986008 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986008
Method and apparatus for identifying instruction boundaries Dec 4, 1997 Issued
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