
John A. Follansbee
Supervisory Patent Examiner (ID: 2573, Phone: (571)272-3964 , Office: P/2400 )
| Most Active Art Unit | 2783 |
| Art Unit(s) | 2154, 2156, 2712, 2302, 2100, 2126, 2783, 2444, 2451, 2127 |
| Total Applications | 601 |
| Issued Applications | 382 |
| Pending Applications | 86 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1557592
[patent_doc_number] => 06401190
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Parallel computing units having special registers storing large bit widths'
[patent_app_type] => B1
[patent_app_number] => 08/913840
[patent_app_country] => US
[patent_app_date] => 1997-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 22931
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/401/06401190.pdf
[firstpage_image] =>[orig_patent_app_number] => 08913840
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/913840 | Parallel computing units having special registers storing large bit widths | Sep 11, 1997 | Issued |
Array
(
[id] => 4252697
[patent_doc_number] => 06076159
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline'
[patent_app_type] => 1
[patent_app_number] => 8/928766
[patent_app_country] => US
[patent_app_date] => 1997-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 5721
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/076/06076159.pdf
[firstpage_image] =>[orig_patent_app_number] => 928766
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/928766 | Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline | Sep 11, 1997 | Issued |
Array
(
[id] => 4239854
[patent_doc_number] => 06012109
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Video capture device with adjustable frame rate based on available bus bandwidth'
[patent_app_type] => 1
[patent_app_number] => 8/926374
[patent_app_country] => US
[patent_app_date] => 1997-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 10828
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/012/06012109.pdf
[firstpage_image] =>[orig_patent_app_number] => 926374
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/926374 | Video capture device with adjustable frame rate based on available bus bandwidth | Sep 8, 1997 | Issued |
Array
(
[id] => 4176976
[patent_doc_number] => 06108705
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Call set-up server'
[patent_app_type] => 1
[patent_app_number] => 8/925858
[patent_app_country] => US
[patent_app_date] => 1997-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 5848
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/108/06108705.pdf
[firstpage_image] =>[orig_patent_app_number] => 925858
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/925858 | Call set-up server | Sep 8, 1997 | Issued |
Array
(
[id] => 3992763
[patent_doc_number] => 05918029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Bus interface slicing mechanism allowing for a control/data-path slice'
[patent_app_type] => 1
[patent_app_number] => 8/999899
[patent_app_country] => US
[patent_app_date] => 1997-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3726
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/918/05918029.pdf
[firstpage_image] =>[orig_patent_app_number] => 999899
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/999899 | Bus interface slicing mechanism allowing for a control/data-path slice | Sep 7, 1997 | Issued |
Array
(
[id] => 1432398
[patent_doc_number] => 06505290
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-07
[patent_title] => 'Method and apparatus for interfacing a processor to a coprocessor'
[patent_app_type] => B1
[patent_app_number] => 08/924518
[patent_app_country] => US
[patent_app_date] => 1997-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 26
[patent_no_of_words] => 7196
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/505/06505290.pdf
[firstpage_image] =>[orig_patent_app_number] => 08924518
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/924518 | Method and apparatus for interfacing a processor to a coprocessor | Sep 4, 1997 | Issued |
Array
(
[id] => 4020819
[patent_doc_number] => 05987494
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Multi-function parallel processing electronic device'
[patent_app_type] => 1
[patent_app_number] => 8/923124
[patent_app_country] => US
[patent_app_date] => 1997-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3864
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/987/05987494.pdf
[firstpage_image] =>[orig_patent_app_number] => 923124
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/923124 | Multi-function parallel processing electronic device | Sep 3, 1997 | Issued |
Array
(
[id] => 4138995
[patent_doc_number] => 06073229
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Computer system having a modular architecture'
[patent_app_type] => 1
[patent_app_number] => 8/921463
[patent_app_country] => US
[patent_app_date] => 1997-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 38
[patent_no_of_words] => 17748
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/073/06073229.pdf
[firstpage_image] =>[orig_patent_app_number] => 921463
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/921463 | Computer system having a modular architecture | Sep 1, 1997 | Issued |
| 08/860152 | MICROPROCESSOR FOR SIMULTANEOUS EXECUTION OF A PLURALITY OF PROGRAMS | Aug 25, 1997 | Abandoned |
Array
(
[id] => 4170889
[patent_doc_number] => 06125390
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-26
[patent_title] => 'Method and apparatus for monitoring and controlling in a network'
[patent_app_type] => 1
[patent_app_number] => 8/918783
[patent_app_country] => US
[patent_app_date] => 1997-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 13381
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/125/06125390.pdf
[firstpage_image] =>[orig_patent_app_number] => 918783
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/918783 | Method and apparatus for monitoring and controlling in a network | Aug 24, 1997 | Issued |
Array
(
[id] => 4351284
[patent_doc_number] => 06314462
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Sub-entry point interface architecture for change management in a computer network'
[patent_app_type] => 1
[patent_app_number] => 8/910858
[patent_app_country] => US
[patent_app_date] => 1997-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 4013
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/314/06314462.pdf
[firstpage_image] =>[orig_patent_app_number] => 910858
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/910858 | Sub-entry point interface architecture for change management in a computer network | Aug 12, 1997 | Issued |
Array
(
[id] => 3970756
[patent_doc_number] => 05999991
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Programmably selectable addresses for expansion cards for a motherboard'
[patent_app_type] => 1
[patent_app_number] => 8/906398
[patent_app_country] => US
[patent_app_date] => 1997-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 22
[patent_no_of_words] => 12576
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/999/05999991.pdf
[firstpage_image] =>[orig_patent_app_number] => 906398
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/906398 | Programmably selectable addresses for expansion cards for a motherboard | Aug 4, 1997 | Issued |
Array
(
[id] => 4210541
[patent_doc_number] => 06044392
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Method and apparatus for performing rounding in a data processor'
[patent_app_type] => 1
[patent_app_number] => 8/905764
[patent_app_country] => US
[patent_app_date] => 1997-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3360
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/044/06044392.pdf
[firstpage_image] =>[orig_patent_app_number] => 905764
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/905764 | Method and apparatus for performing rounding in a data processor | Aug 3, 1997 | Issued |
Array
(
[id] => 4132355
[patent_doc_number] => 06047304
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Method and apparatus for performing lane arithmetic to perform network processing'
[patent_app_type] => 1
[patent_app_number] => 8/902396
[patent_app_country] => US
[patent_app_date] => 1997-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2989
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/047/06047304.pdf
[firstpage_image] =>[orig_patent_app_number] => 902396
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/902396 | Method and apparatus for performing lane arithmetic to perform network processing | Jul 28, 1997 | Issued |
Array
(
[id] => 4100630
[patent_doc_number] => 06018769
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Integrated network installation system'
[patent_app_type] => 1
[patent_app_number] => 8/895555
[patent_app_country] => US
[patent_app_date] => 1997-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 52
[patent_figures_cnt] => 67
[patent_no_of_words] => 21244
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/018/06018769.pdf
[firstpage_image] =>[orig_patent_app_number] => 895555
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895555 | Integrated network installation system | Jul 15, 1997 | Issued |
Array
(
[id] => 4082224
[patent_doc_number] => 05867734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Multiple-reader multiple-writer queue for a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/889837
[patent_app_country] => US
[patent_app_date] => 1997-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4352
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/867/05867734.pdf
[firstpage_image] =>[orig_patent_app_number] => 889837
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/889837 | Multiple-reader multiple-writer queue for a computer system | Jul 7, 1997 | Issued |
Array
(
[id] => 4388507
[patent_doc_number] => 06275923
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-14
[patent_title] => 'Data processing method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/883228
[patent_app_country] => US
[patent_app_date] => 1997-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4533
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/275/06275923.pdf
[firstpage_image] =>[orig_patent_app_number] => 883228
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/883228 | Data processing method and apparatus | Jun 25, 1997 | Issued |
Array
(
[id] => 4118431
[patent_doc_number] => 06098165
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Fetching and handling a bundle of instructions comprising instructions and non-complex instructions'
[patent_app_type] => 1
[patent_app_number] => 8/881908
[patent_app_country] => US
[patent_app_date] => 1997-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5837
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/098/06098165.pdf
[firstpage_image] =>[orig_patent_app_number] => 881908
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881908 | Fetching and handling a bundle of instructions comprising instructions and non-complex instructions | Jun 24, 1997 | Issued |
Array
(
[id] => 4211610
[patent_doc_number] => 06044452
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Method for symmetrically processing'
[patent_app_type] => 1
[patent_app_number] => 8/880085
[patent_app_country] => US
[patent_app_date] => 1997-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1944
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/044/06044452.pdf
[firstpage_image] =>[orig_patent_app_number] => 880085
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880085 | Method for symmetrically processing | Jun 19, 1997 | Issued |
Array
(
[id] => 4132805
[patent_doc_number] => 06047333
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Node adapter including hardware arrangement for filtering broadcast data on network'
[patent_app_type] => 1
[patent_app_number] => 8/867874
[patent_app_country] => US
[patent_app_date] => 1997-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4315
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/047/06047333.pdf
[firstpage_image] =>[orig_patent_app_number] => 867874
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/867874 | Node adapter including hardware arrangement for filtering broadcast data on network | Jun 2, 1997 | Issued |