Search

John A. Follansbee

Supervisory Patent Examiner (ID: 2573, Phone: (571)272-3964 , Office: P/2400 )

Most Active Art Unit
2783
Art Unit(s)
2154, 2156, 2712, 2302, 2100, 2126, 2783, 2444, 2451, 2127
Total Applications
601
Issued Applications
382
Pending Applications
86
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3919114 [patent_doc_number] => 05752030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Program execution control in parallel processor system for parallel execution of plural jobs by selected number of processors' [patent_app_type] => 1 [patent_app_number] => 8/101993 [patent_app_country] => US [patent_app_date] => 1993-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4630 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 544 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752030.pdf [firstpage_image] =>[orig_patent_app_number] => 101993 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/101993
Program execution control in parallel processor system for parallel execution of plural jobs by selected number of processors Aug 3, 1993 Issued
Array ( [id] => 1557482 [patent_doc_number] => 06401158 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Apparatus for providing a CPU cluster via a disk I/O bus using a CPU brick which fits into a disk cavity' [patent_app_type] => B1 [patent_app_number] => 08/092622 [patent_app_country] => US [patent_app_date] => 1993-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3517 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401158.pdf [firstpage_image] =>[orig_patent_app_number] => 08092622 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/092622
Apparatus for providing a CPU cluster via a disk I/O bus using a CPU brick which fits into a disk cavity Jul 15, 1993 Issued
Array ( [id] => 3473823 [patent_doc_number] => 05392445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Data storing system and data transfer method with a plurality of disk units' [patent_app_type] => 1 [patent_app_number] => 8/089144 [patent_app_country] => US [patent_app_date] => 1993-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3367 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392445.pdf [firstpage_image] =>[orig_patent_app_number] => 089144 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/089144
Data storing system and data transfer method with a plurality of disk units Jul 6, 1993 Issued
Array ( [id] => 3973523 [patent_doc_number] => 05978897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Sequence operation processor employing multi-port RAMs for simultaneously reading and writing' [patent_app_type] => 1 [patent_app_number] => 8/070296 [patent_app_country] => US [patent_app_date] => 1993-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4496 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978897.pdf [firstpage_image] =>[orig_patent_app_number] => 070296 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/070296
Sequence operation processor employing multi-port RAMs for simultaneously reading and writing Jun 1, 1993 Issued
08/050196 PROCESS FOR TRANSMITTING DATA IN A DATA PROCESSING SYSTEM WITH DISTRIBUTED COMPUTER NODES, COMMUNICATING VIA A SERIAL DATA BUS, BETWEEN WHICH DATA MESSAGES ARE EXCHANGED, TESTED FOR ACCEPTANCE IN A COMPUTER NODE, AND STORED TEMPORARILY May 3, 1993 Pending
Array ( [id] => 4021792 [patent_doc_number] => 06006090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Providing roaming capability for mobile computers in a standard network' [patent_app_type] => 1 [patent_app_number] => 8/053191 [patent_app_country] => US [patent_app_date] => 1993-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2053 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006090.pdf [firstpage_image] =>[orig_patent_app_number] => 053191 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/053191
Providing roaming capability for mobile computers in a standard network Apr 27, 1993 Issued
08/049806 INFORMATION PROCESSING APPARATUS HAVING AN INITIALIZING EMULATION PROGRAM TO PROVIDE COMPATIBILITY BETWEEN DIFFERENT Apr 19, 1993 Pending
Array ( [id] => 3778404 [patent_doc_number] => 05845078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Network integrated construction system, method of installing network connection machines, and method of setting network parameters' [patent_app_type] => 1 [patent_app_number] => 8/046942 [patent_app_country] => US [patent_app_date] => 1993-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 124 [patent_figures_cnt] => 224 [patent_no_of_words] => 56824 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845078.pdf [firstpage_image] =>[orig_patent_app_number] => 046942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/046942
Network integrated construction system, method of installing network connection machines, and method of setting network parameters Apr 15, 1993 Issued
Array ( [id] => 3970045 [patent_doc_number] => 05958037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Apparatus and method for identifying the features and the origin of a computer microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/023916 [patent_app_country] => US [patent_app_date] => 1993-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8014 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958037.pdf [firstpage_image] =>[orig_patent_app_number] => 023916 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/023916
Apparatus and method for identifying the features and the origin of a computer microprocessor Feb 25, 1993 Issued
Array ( [id] => 3736962 [patent_doc_number] => 05701501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Apparatus and method for executing an atomic instruction' [patent_app_type] => 1 [patent_app_number] => 8/023693 [patent_app_country] => US [patent_app_date] => 1993-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1486 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701501.pdf [firstpage_image] =>[orig_patent_app_number] => 023693 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/023693
Apparatus and method for executing an atomic instruction Feb 25, 1993 Issued
Array ( [id] => 3776719 [patent_doc_number] => 05742839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Coprocessor for performing an arithmetic operation by automatically reading data from an external memory' [patent_app_type] => 1 [patent_app_number] => 8/011762 [patent_app_country] => US [patent_app_date] => 1993-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10397 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742839.pdf [firstpage_image] =>[orig_patent_app_number] => 011762 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/011762
Coprocessor for performing an arithmetic operation by automatically reading data from an external memory Jan 31, 1993 Issued
Array ( [id] => 3927993 [patent_doc_number] => 06002798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method and apparatus for creating, indexing and viewing abstracted documents' [patent_app_type] => 1 [patent_app_number] => 8/005444 [patent_app_country] => US [patent_app_date] => 1993-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5695 [patent_no_of_claims] => 118 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002798.pdf [firstpage_image] =>[orig_patent_app_number] => 005444 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/005444
Method and apparatus for creating, indexing and viewing abstracted documents Jan 18, 1993 Issued
Array ( [id] => 3668117 [patent_doc_number] => 05623683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Two stage binary multiplier' [patent_app_type] => 1 [patent_app_number] => 7/998382 [patent_app_country] => US [patent_app_date] => 1992-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4476 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623683.pdf [firstpage_image] =>[orig_patent_app_number] => 998382 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/998382
Two stage binary multiplier Dec 29, 1992 Issued
07/996465 SECURE COMPOSITE COMPUTER NETWORK Dec 23, 1992 Abandoned
Array ( [id] => 4103350 [patent_doc_number] => 06026443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Multi-virtual DMA channels, multi-bandwidth groups, host based cellification and reassembly, and asynchronous transfer mode network interface' [patent_app_type] => 1 [patent_app_number] => 7/995591 [patent_app_country] => US [patent_app_date] => 1992-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10496 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026443.pdf [firstpage_image] =>[orig_patent_app_number] => 995591 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/995591
Multi-virtual DMA channels, multi-bandwidth groups, host based cellification and reassembly, and asynchronous transfer mode network interface Dec 21, 1992 Issued
Array ( [id] => 3718968 [patent_doc_number] => 05655131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'SIMD architecture for connection to host processor\'s bus' [patent_app_type] => 1 [patent_app_number] => 7/993256 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 20201 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 591 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/655/05655131.pdf [firstpage_image] =>[orig_patent_app_number] => 993256 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993256
SIMD architecture for connection to host processor's bus Dec 17, 1992 Issued
Array ( [id] => 3894436 [patent_doc_number] => 05826033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Parallel computer apparatus and method for performing all-to-all communications among processing elements' [patent_app_type] => 1 [patent_app_number] => 7/982579 [patent_app_country] => US [patent_app_date] => 1992-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 9921 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/826/05826033.pdf [firstpage_image] =>[orig_patent_app_number] => 982579 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/982579
Parallel computer apparatus and method for performing all-to-all communications among processing elements Nov 26, 1992 Issued
Array ( [id] => 4100659 [patent_doc_number] => 06018771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Dynamic assignment of multicast network addresses' [patent_app_type] => 1 [patent_app_number] => 7/981274 [patent_app_country] => US [patent_app_date] => 1992-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4245 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018771.pdf [firstpage_image] =>[orig_patent_app_number] => 981274 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/981274
Dynamic assignment of multicast network addresses Nov 24, 1992 Issued
07/971566 INFORMATION PROCESSING SYSTEM HAVING A CONFIGURATION MANAGEMENT SYSTEM FOR MANAGING THE SOFTWARE OF THE INFORMATION PROCESSING SYSTEM Nov 4, 1992 Abandoned
07/968398 DIGITAL COMPUTER SYSTEM CAPABLE OF PROCESSING A PLURALITY OF INSTRUCTIONS IN PARALLEL BASED ON A VLIM ARCHITECTURE Oct 28, 1992 Abandoned
Menu