Search

John A. Follansbee

Supervisory Patent Examiner (ID: 2573, Phone: (571)272-3964 , Office: P/2400 )

Most Active Art Unit
2783
Art Unit(s)
2154, 2156, 2712, 2302, 2100, 2126, 2783, 2444, 2451, 2127
Total Applications
601
Issued Applications
382
Pending Applications
86
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1506060 [patent_doc_number] => 06487675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-26 [patent_title] => 'Processor having execution core sections operating at different clock rates' [patent_app_type] => B2 [patent_app_number] => 09/775383 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9187 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487675.pdf [firstpage_image] =>[orig_patent_app_number] => 09775383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775383
Processor having execution core sections operating at different clock rates Feb 1, 2001 Issued
Array ( [id] => 6019826 [patent_doc_number] => 20020103921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method and system for routing broadband internet traffic' [patent_app_type] => new [patent_app_number] => 09/774016 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8099 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20020103921.pdf [firstpage_image] =>[orig_patent_app_number] => 09774016 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774016
Method and system for routing broadband internet traffic Jan 30, 2001 Abandoned
Array ( [id] => 6874980 [patent_doc_number] => 20010000046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-03-15 [patent_title] => 'Architecture for a processor complex of an arrayed pipelined processing engine' [patent_app_type] => new-utility [patent_app_number] => 09/727068 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7466 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000046.pdf [firstpage_image] =>[orig_patent_app_number] => 09727068 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/727068
Architecture for a process complex of an arrayed pipelined processing engine Nov 29, 2000 Issued
Array ( [id] => 1475031 [patent_doc_number] => 06408384 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Cache fencing for interpretive environments' [patent_app_type] => B1 [patent_app_number] => 09/705370 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408384.pdf [firstpage_image] =>[orig_patent_app_number] => 09705370 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705370
Cache fencing for interpretive environments Nov 2, 2000 Issued
Array ( [id] => 1497871 [patent_doc_number] => 06343357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Microcomputer and dividing circuit' [patent_app_type] => B1 [patent_app_number] => 09/632332 [patent_app_country] => US [patent_app_date] => 2000-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 87 [patent_figures_cnt] => 100 [patent_no_of_words] => 37436 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343357.pdf [firstpage_image] =>[orig_patent_app_number] => 09632332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632332
Microcomputer and dividing circuit Aug 2, 2000 Issued
Array ( [id] => 4324611 [patent_doc_number] => 06327647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method and apparatus for interfacing a processor to a coprocessor' [patent_app_type] => 1 [patent_app_number] => 9/609260 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 7114 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327647.pdf [firstpage_image] =>[orig_patent_app_number] => 609260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609260
Method and apparatus for interfacing a processor to a coprocessor Jun 29, 2000 Issued
Array ( [id] => 7634978 [patent_doc_number] => 06381688 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Serial port for a hose adapter integrated circuit using a single terminal' [patent_app_type] => B1 [patent_app_number] => 09/579863 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 38 [patent_no_of_words] => 24075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381688.pdf [firstpage_image] =>[orig_patent_app_number] => 09579863 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/579863
Serial port for a hose adapter integrated circuit using a single terminal May 24, 2000 Issued
Array ( [id] => 4381843 [patent_doc_number] => 06256745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Processor having execution core sections operating at different clock rates' [patent_app_type] => 1 [patent_app_number] => 9/527065 [patent_app_country] => US [patent_app_date] => 2000-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9101 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256745.pdf [firstpage_image] =>[orig_patent_app_number] => 527065 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/527065
Processor having execution core sections operating at different clock rates Mar 15, 2000 Issued
Array ( [id] => 1218211 [patent_doc_number] => 06711666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'IBM PC compatible multi-chip module' [patent_app_type] => B1 [patent_app_number] => 09/524858 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11236 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711666.pdf [firstpage_image] =>[orig_patent_app_number] => 09524858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/524858
IBM PC compatible multi-chip module Mar 13, 2000 Issued
Array ( [id] => 7644182 [patent_doc_number] => 06473792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Method of simulating broadband internet content downloads' [patent_app_type] => B1 [patent_app_number] => 09/523253 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5913 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473792.pdf [firstpage_image] =>[orig_patent_app_number] => 09523253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/523253
Method of simulating broadband internet content downloads Mar 9, 2000 Issued
Array ( [id] => 1408651 [patent_doc_number] => 06557036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Methods and apparatus for site wide monitoring of electronic mail systems' [patent_app_type] => B1 [patent_app_number] => 09/520865 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557036.pdf [firstpage_image] =>[orig_patent_app_number] => 09520865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520865
Methods and apparatus for site wide monitoring of electronic mail systems Mar 6, 2000 Issued
Array ( [id] => 1459874 [patent_doc_number] => 06463469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Computer-based RDS/MBS receiver system for use with radio broadcast signal' [patent_app_type] => B1 [patent_app_number] => 09/484334 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4347 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463469.pdf [firstpage_image] =>[orig_patent_app_number] => 09484334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/484334
Computer-based RDS/MBS receiver system for use with radio broadcast signal Jan 17, 2000 Issued
Array ( [id] => 4273888 [patent_doc_number] => 06209087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Data processor with multiple compare extension instruction' [patent_app_type] => 1 [patent_app_number] => 9/484158 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10729 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209087.pdf [firstpage_image] =>[orig_patent_app_number] => 484158 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/484158
Data processor with multiple compare extension instruction Jan 17, 2000 Issued
Array ( [id] => 4292397 [patent_doc_number] => 06247110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem' [patent_app_type] => 1 [patent_app_number] => 9/481902 [patent_app_country] => US [patent_app_date] => 2000-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3404 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247110.pdf [firstpage_image] =>[orig_patent_app_number] => 481902 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481902
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem Jan 11, 2000 Issued
Array ( [id] => 1572143 [patent_doc_number] => 06377997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Dynamic assignment of multicast network addresses' [patent_app_type] => B1 [patent_app_number] => 09/480904 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4249 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377997.pdf [firstpage_image] =>[orig_patent_app_number] => 09480904 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/480904
Dynamic assignment of multicast network addresses Jan 10, 2000 Issued
Array ( [id] => 1572261 [patent_doc_number] => 06378023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Interrupt descriptor cache for a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/481005 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378023.pdf [firstpage_image] =>[orig_patent_app_number] => 09481005 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481005
Interrupt descriptor cache for a microprocessor Jan 9, 2000 Issued
Array ( [id] => 1508957 [patent_doc_number] => 06467004 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Pipelined semiconductor devices suitable for ultra large scale integration' [patent_app_type] => B1 [patent_app_number] => 09/477448 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 7049 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467004.pdf [firstpage_image] =>[orig_patent_app_number] => 09477448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477448
Pipelined semiconductor devices suitable for ultra large scale integration Jan 3, 2000 Issued
Array ( [id] => 1466743 [patent_doc_number] => 06351822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method and apparatus for remapping read only memory locations' [patent_app_type] => B1 [patent_app_number] => 09/469937 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5022 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351822.pdf [firstpage_image] =>[orig_patent_app_number] => 09469937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469937
Method and apparatus for remapping read only memory locations Dec 20, 1999 Issued
Array ( [id] => 1587340 [patent_doc_number] => 06425039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-23 [patent_title] => 'Accessing exception handlers without translating the address' [patent_app_type] => B2 [patent_app_number] => 09/450894 [patent_app_country] => US [patent_app_date] => 1999-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 15222 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425039.pdf [firstpage_image] =>[orig_patent_app_number] => 09450894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/450894
Accessing exception handlers without translating the address Nov 28, 1999 Issued
Array ( [id] => 4374416 [patent_doc_number] => 06170024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Adjusting the volume by a keyboard via an independent control circuit, independent of a host computer' [patent_app_type] => 1 [patent_app_number] => 9/448186 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8679 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170024.pdf [firstpage_image] =>[orig_patent_app_number] => 448186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448186
Adjusting the volume by a keyboard via an independent control circuit, independent of a host computer Nov 22, 1999 Issued
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