
John A. Follansbee
Supervisory Patent Examiner (ID: 2573, Phone: (571)272-3964 , Office: P/2400 )
| Most Active Art Unit | 2783 |
| Art Unit(s) | 2154, 2156, 2712, 2302, 2100, 2126, 2783, 2444, 2451, 2127 |
| Total Applications | 601 |
| Issued Applications | 382 |
| Pending Applications | 86 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1501491
[patent_doc_number] => 06405273
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Data processing device with memory coupling unit'
[patent_app_type] => B1
[patent_app_number] => 09/192170
[patent_app_country] => US
[patent_app_date] => 1998-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 7043
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/405/06405273.pdf
[firstpage_image] =>[orig_patent_app_number] => 09192170
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/192170 | Data processing device with memory coupling unit | Nov 12, 1998 | Issued |
Array
(
[id] => 1438601
[patent_doc_number] => 06356939
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-12
[patent_title] => 'Interactive theater and feature presentation system'
[patent_app_type] => B1
[patent_app_number] => 09/189256
[patent_app_country] => US
[patent_app_date] => 1998-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4133
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/356/06356939.pdf
[firstpage_image] =>[orig_patent_app_number] => 09189256
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/189256 | Interactive theater and feature presentation system | Nov 9, 1998 | Issued |
Array
(
[id] => 4162663
[patent_doc_number] => 06032253
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Data processor with multiple compare extension instruction'
[patent_app_type] => 1
[patent_app_number] => 9/188624
[patent_app_country] => US
[patent_app_date] => 1998-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10736
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/032/06032253.pdf
[firstpage_image] =>[orig_patent_app_number] => 188624
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/188624 | Data processor with multiple compare extension instruction | Nov 8, 1998 | Issued |
Array
(
[id] => 4166157
[patent_doc_number] => 06065027
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Data processor with up pointer walk trie traversal instruction set extension'
[patent_app_type] => 1
[patent_app_number] => 9/188850
[patent_app_country] => US
[patent_app_date] => 1998-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10740
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/065/06065027.pdf
[firstpage_image] =>[orig_patent_app_number] => 188850
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/188850 | Data processor with up pointer walk trie traversal instruction set extension | Nov 8, 1998 | Issued |
Array
(
[id] => 4380229
[patent_doc_number] => 06192491
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Data processor with CRC instruction set extension'
[patent_app_type] => 1
[patent_app_number] => 9/189016
[patent_app_country] => US
[patent_app_date] => 1998-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10728
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/192/06192491.pdf
[firstpage_image] =>[orig_patent_app_number] => 189016
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/189016 | Data processor with CRC instruction set extension | Nov 8, 1998 | Issued |
Array
(
[id] => 4279289
[patent_doc_number] => 06205487
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Data processor with bit unstuffing instruction set extension'
[patent_app_type] => 1
[patent_app_number] => 9/186998
[patent_app_country] => US
[patent_app_date] => 1998-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10732
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/205/06205487.pdf
[firstpage_image] =>[orig_patent_app_number] => 186998
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/186998 | Data processor with bit unstuffing instruction set extension | Nov 5, 1998 | Issued |
Array
(
[id] => 4309623
[patent_doc_number] => 06212569
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Data processor with bit stuffing instruction set extension'
[patent_app_type] => 1
[patent_app_number] => 9/187438
[patent_app_country] => US
[patent_app_date] => 1998-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10739
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/212/06212569.pdf
[firstpage_image] =>[orig_patent_app_number] => 187438
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/187438 | Data processor with bit stuffing instruction set extension | Nov 5, 1998 | Issued |
Array
(
[id] => 4332872
[patent_doc_number] => 06317790
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Method and system for interrupting page delivery operations in a web environment'
[patent_app_type] => 1
[patent_app_number] => 9/187293
[patent_app_country] => US
[patent_app_date] => 1998-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7601
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/317/06317790.pdf
[firstpage_image] =>[orig_patent_app_number] => 187293
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/187293 | Method and system for interrupting page delivery operations in a web environment | Nov 4, 1998 | Issued |
Array
(
[id] => 6606769
[patent_doc_number] => 20020042874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-11
[patent_title] => 'APPARATUS AND METHOD TO CHANGE PROCESSOR PRIVILEGE WITHOUT PIPELINE FLUSH'
[patent_app_type] => new
[patent_app_number] => 09/183421
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5440
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20020042874.pdf
[firstpage_image] =>[orig_patent_app_number] => 09183421
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183421 | Apparatus and method to change processor privilege without pipeline flush | Oct 29, 1998 | Issued |
Array
(
[id] => 4404107
[patent_doc_number] => 06263417
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Method of implementing vector operation using a processor chip which is provided with a vector unit'
[patent_app_type] => 1
[patent_app_number] => 9/182216
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1607
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/263/06263417.pdf
[firstpage_image] =>[orig_patent_app_number] => 182216
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182216 | Method of implementing vector operation using a processor chip which is provided with a vector unit | Oct 29, 1998 | Issued |
Array
(
[id] => 1472009
[patent_doc_number] => 06460134
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Method and apparatus for a late pipeline enhanced floating point unit'
[patent_app_type] => B1
[patent_app_number] => 09/181406
[patent_app_country] => US
[patent_app_date] => 1998-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 9448
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/460/06460134.pdf
[firstpage_image] =>[orig_patent_app_number] => 09181406
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/181406 | Method and apparatus for a late pipeline enhanced floating point unit | Oct 27, 1998 | Issued |
Array
(
[id] => 4269556
[patent_doc_number] => 06223217
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Distributed object networking service'
[patent_app_type] => 1
[patent_app_number] => 9/179077
[patent_app_country] => US
[patent_app_date] => 1998-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 11156
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/223/06223217.pdf
[firstpage_image] =>[orig_patent_app_number] => 179077
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/179077 | Distributed object networking service | Oct 25, 1998 | Issued |
Array
(
[id] => 1557603
[patent_doc_number] => 06401193
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Dynamic data prefetching based on program counter and addressing mode'
[patent_app_type] => B1
[patent_app_number] => 09/178052
[patent_app_country] => US
[patent_app_date] => 1998-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4989
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/401/06401193.pdf
[firstpage_image] =>[orig_patent_app_number] => 09178052
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/178052 | Dynamic data prefetching based on program counter and addressing mode | Oct 25, 1998 | Issued |
Array
(
[id] => 4267973
[patent_doc_number] => 06138136
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Signal processor'
[patent_app_type] => 1
[patent_app_number] => 9/011673
[patent_app_country] => US
[patent_app_date] => 1998-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 7207
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/138/06138136.pdf
[firstpage_image] =>[orig_patent_app_number] => 011673
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/011673 | Signal processor | Oct 22, 1998 | Issued |
Array
(
[id] => 1497864
[patent_doc_number] => 06343356
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-29
[patent_title] => 'Methods and apparatus for dynamic instruction controlled reconfiguration register file with extended precision'
[patent_app_type] => B1
[patent_app_number] => 09/169255
[patent_app_country] => US
[patent_app_date] => 1998-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4476
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/343/06343356.pdf
[firstpage_image] =>[orig_patent_app_number] => 09169255
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/169255 | Methods and apparatus for dynamic instruction controlled reconfiguration register file with extended precision | Oct 8, 1998 | Issued |
Array
(
[id] => 4371334
[patent_doc_number] => 06216220
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-10
[patent_title] => 'Multithreaded data processing method with long latency subinstructions'
[patent_app_type] => 1
[patent_app_number] => 9/168068
[patent_app_country] => US
[patent_app_date] => 1998-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3559
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/216/06216220.pdf
[firstpage_image] =>[orig_patent_app_number] => 168068
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/168068 | Multithreaded data processing method with long latency subinstructions | Oct 7, 1998 | Issued |
Array
(
[id] => 4280044
[patent_doc_number] => 06205535
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Branch instruction having different field lengths for unconditional and conditional displacements'
[patent_app_type] => 1
[patent_app_number] => 9/167029
[patent_app_country] => US
[patent_app_date] => 1998-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 87
[patent_figures_cnt] => 113
[patent_no_of_words] => 38589
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/205/06205535.pdf
[firstpage_image] =>[orig_patent_app_number] => 167029
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/167029 | Branch instruction having different field lengths for unconditional and conditional displacements | Oct 5, 1998 | Issued |
Array
(
[id] => 1553810
[patent_doc_number] => 06347369
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-12
[patent_title] => 'Method and circuit for single cycle multiple branch history table access'
[patent_app_type] => B1
[patent_app_number] => 09/159900
[patent_app_country] => US
[patent_app_date] => 1998-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 9939
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/347/06347369.pdf
[firstpage_image] =>[orig_patent_app_number] => 09159900
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/159900 | Method and circuit for single cycle multiple branch history table access | Sep 23, 1998 | Issued |
Array
(
[id] => 4421542
[patent_doc_number] => 06233602
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-15
[patent_title] => 'Dynamically allocating server processes to client processes'
[patent_app_type] => 1
[patent_app_number] => 9/158935
[patent_app_country] => US
[patent_app_date] => 1998-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 7692
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/233/06233602.pdf
[firstpage_image] =>[orig_patent_app_number] => 158935
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/158935 | Dynamically allocating server processes to client processes | Sep 21, 1998 | Issued |
Array
(
[id] => 4423904
[patent_doc_number] => 06240521
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Sleep mode transition between processors sharing an instruction set and an address space'
[patent_app_type] => 1
[patent_app_number] => 9/151133
[patent_app_country] => US
[patent_app_date] => 1998-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3246
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/240/06240521.pdf
[firstpage_image] =>[orig_patent_app_number] => 151133
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/151133 | Sleep mode transition between processors sharing an instruction set and an address space | Sep 9, 1998 | Issued |