
John A. Lane
Examiner (ID: 16902, Phone: (571)272-4208 , Office: P/2139 )
| Most Active Art Unit | 2139 |
| Art Unit(s) | 2309, 2139, 2185, 2188, 2751, 2189, 2186, 2305, 2303, 2312 |
| Total Applications | 2052 |
| Issued Applications | 1798 |
| Pending Applications | 47 |
| Abandoned Applications | 220 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10941515
[patent_doc_number] => 20140344536
[patent_country] => US
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[patent_issue_date] => 2014-11-20
[patent_title] => 'STORAGE SYSTEMS THAT CREATE SNAPSHOT QUEUES'
[patent_app_type] => utility
[patent_app_number] => 13/895086
[patent_app_country] => US
[patent_app_date] => 2013-05-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/895086 | Storage systems that create snapshot queues | May 14, 2013 | Issued |
Array
(
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[patent_doc_number] => 20130254471
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[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'DEVICE AND MEMORY SYSTEM FOR MEMORY MANAGEMENT USING ACCESS FREQUENCY INFORMATION'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/890891 | Device and memory system for swappable memory | May 8, 2013 | Issued |
Array
(
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[patent_doc_number] => 20140325142
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[patent_issue_date] => 2014-10-30
[patent_title] => 'Input/Output De-Duplication Based on Variable-Size Chunks'
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Array
(
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[patent_issue_date] => 2015-11-24
[patent_title] => 'Storage system with load balancing mechanism and method of operation thereof'
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Array
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[patent_issue_date] => 2015-11-24
[patent_title] => 'Simultaneously accessible memory device and method for using the same'
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Array
(
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[patent_doc_number] => 20140003131
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[patent_kind] => A1
[patent_issue_date] => 2014-01-02
[patent_title] => 'MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/860825 | Multi-column addressing mode memory system including an integrated circuit memory device | Apr 10, 2013 | Issued |
Array
(
[id] => 10680430
[patent_doc_number] => 20160026576
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[patent_issue_date] => 2016-01-28
[patent_title] => 'IMPLEMENTING COHERENCY WITH REFLECTIVE MEMORY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/763943 | Implementing coherency with reflective memory | Mar 27, 2013 | Issued |
Array
(
[id] => 9096375
[patent_doc_number] => 20130275686
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[patent_issue_date] => 2013-10-17
[patent_title] => 'MULTIPROCESSOR SYSTEM AND METHOD FOR MANAGING CACHE MEMORY THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/793023 | Multiprocessor system and method for managing cache memory thereof | Mar 10, 2013 | Issued |
Array
(
[id] => 10131055
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Array
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[patent_title] => 'Apparatuses and methods for a memory die architecture including an interface memory'
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Array
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Array
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/787650 | Migrating virtual machines across sites | Mar 5, 2013 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/730507 | Apparatus and method for implementing a scratchpad memory using priority hint | Dec 27, 2012 | Issued |
Array
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Array
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