Search

John A. Lane

Examiner (ID: 16902, Phone: (571)272-4208 , Office: P/2139 )

Most Active Art Unit
2139
Art Unit(s)
2309, 2139, 2185, 2188, 2751, 2189, 2186, 2305, 2303, 2312
Total Applications
2052
Issued Applications
1798
Pending Applications
47
Abandoned Applications
220

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5806361 [patent_doc_number] => 20060092714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Semiconductor memory device with simplified data control signals' [patent_app_type] => utility [patent_app_number] => 11/044976 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4702 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20060092714.pdf [firstpage_image] =>[orig_patent_app_number] => 11044976 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044976
Semiconductor memory device with simplified data control signals Jan 25, 2005 Issued
Array ( [id] => 5879113 [patent_doc_number] => 20060168406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Balanced bitcell design for a multi-port register file' [patent_app_type] => utility [patent_app_number] => 11/042026 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4868 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20060168406.pdf [firstpage_image] =>[orig_patent_app_number] => 11042026 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042026
Balanced bitcell for a multi-port register file Jan 24, 2005 Issued
Array ( [id] => 7049636 [patent_doc_number] => 20050185523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Storage apparatus with a function for displaying volume information' [patent_app_type] => utility [patent_app_number] => 11/028622 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2012 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20050185523.pdf [firstpage_image] =>[orig_patent_app_number] => 11028622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/028622
Storage apparatus with a function for displaying volume information Jan 4, 2005 Abandoned
Array ( [id] => 929608 [patent_doc_number] => 07315920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Circuit and method for protecting vector tags in high performance microprocessors' [patent_app_type] => utility [patent_app_number] => 11/028293 [patent_app_country] => US [patent_app_date] => 2005-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5300 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315920.pdf [firstpage_image] =>[orig_patent_app_number] => 11028293 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/028293
Circuit and method for protecting vector tags in high performance microprocessors Jan 3, 2005 Issued
Array ( [id] => 877493 [patent_doc_number] => 07363440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-22 [patent_title] => 'System and method for dynamically accessing memory while under normal functional operating conditions' [patent_app_type] => utility [patent_app_number] => 11/026843 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9023 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/363/07363440.pdf [firstpage_image] =>[orig_patent_app_number] => 11026843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026843
System and method for dynamically accessing memory while under normal functional operating conditions Dec 29, 2004 Issued
Array ( [id] => 823321 [patent_doc_number] => 07409495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-05 [patent_title] => 'Method and apparatus for providing a temporal storage appliance with block virtualization in storage networks' [patent_app_type] => utility [patent_app_number] => 11/020863 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6287 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/409/07409495.pdf [firstpage_image] =>[orig_patent_app_number] => 11020863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020863
Method and apparatus for providing a temporal storage appliance with block virtualization in storage networks Dec 21, 2004 Issued
Array ( [id] => 731232 [patent_doc_number] => 07047391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'System and method for re-ordering memory references for access to memory' [patent_app_type] => utility [patent_app_number] => 11/019979 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3011 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/047/07047391.pdf [firstpage_image] =>[orig_patent_app_number] => 11019979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019979
System and method for re-ordering memory references for access to memory Dec 20, 2004 Issued
Array ( [id] => 877531 [patent_doc_number] => 07363454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Storage pool space allocation across multiple locations' [patent_app_type] => utility [patent_app_number] => 11/009210 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6411 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/363/07363454.pdf [firstpage_image] =>[orig_patent_app_number] => 11009210 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009210
Storage pool space allocation across multiple locations Dec 9, 2004 Issued
Array ( [id] => 5190642 [patent_doc_number] => 20070168951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Java smart card chip having memory area reserved for global variables' [patent_app_type] => utility [patent_app_number] => 10/582118 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4124 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168951.pdf [firstpage_image] =>[orig_patent_app_number] => 10582118 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/582118
Java smart card chip having memory area reserved for global variables Dec 2, 2004 Issued
Array ( [id] => 5717139 [patent_doc_number] => 20060080502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Storage apparatus' [patent_app_type] => utility [patent_app_number] => 10/998780 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 17606 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20060080502.pdf [firstpage_image] =>[orig_patent_app_number] => 10998780 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998780
Storage apparatus having virtual-to-actual device addressing scheme Nov 29, 2004 Issued
Array ( [id] => 873382 [patent_doc_number] => 07366820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method' [patent_app_type] => utility [patent_app_number] => 10/999065 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3481 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/366/07366820.pdf [firstpage_image] =>[orig_patent_app_number] => 10999065 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999065
Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method Nov 29, 2004 Issued
Array ( [id] => 885577 [patent_doc_number] => 07356658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Snapshot system' [patent_app_type] => utility [patent_app_number] => 10/998755 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 13063 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/356/07356658.pdf [firstpage_image] =>[orig_patent_app_number] => 10998755 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998755
Snapshot system Nov 29, 2004 Issued
Array ( [id] => 5822042 [patent_doc_number] => 20060026355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Cache memory and method for controlling cache memory' [patent_app_type] => utility [patent_app_number] => 10/998561 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4567 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026355.pdf [firstpage_image] =>[orig_patent_app_number] => 10998561 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998561
Cache memory and method to maintain cache-coherence between cache memory units Nov 29, 2004 Issued
Array ( [id] => 929613 [patent_doc_number] => 07315925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Disabling access based on location' [patent_app_type] => utility [patent_app_number] => 10/555308 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 9529 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315925.pdf [firstpage_image] =>[orig_patent_app_number] => 10555308 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/555308
Disabling access based on location Nov 9, 2004 Issued
Array ( [id] => 5906856 [patent_doc_number] => 20060047931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method and program for creating a snapshot, and storage system' [patent_app_type] => utility [patent_app_number] => 10/979186 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20060047931.pdf [firstpage_image] =>[orig_patent_app_number] => 10979186 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/979186
Method and program for creating a snapshot, and storage system Nov 2, 2004 Issued
Array ( [id] => 407125 [patent_doc_number] => 07290084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Fast collision detection for a hashed content addressable memory (CAM) using a random access memory' [patent_app_type] => utility [patent_app_number] => 10/980858 [patent_app_country] => US [patent_app_date] => 2004-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8057 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/290/07290084.pdf [firstpage_image] =>[orig_patent_app_number] => 10980858 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980858
Fast collision detection for a hashed content addressable memory (CAM) using a random access memory Nov 1, 2004 Issued
Array ( [id] => 5809308 [patent_doc_number] => 20060095663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method and computer program product for combining resources of multiple BIOS ROMS and managing them as a single entity' [patent_app_type] => utility [patent_app_number] => 10/977945 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3479 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095663.pdf [firstpage_image] =>[orig_patent_app_number] => 10977945 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/977945
Method and computer program product for combining resources of multiple BIOS ROMS and managing them as a single entity Oct 31, 2004 Issued
Array ( [id] => 444336 [patent_doc_number] => 07260692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-08-21 [patent_title] => 'Methods and apparatus for accessing trace data' [patent_app_type] => utility [patent_app_number] => 10/978505 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 14784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/260/07260692.pdf [firstpage_image] =>[orig_patent_app_number] => 10978505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/978505
Methods and apparatus for accessing trace data Oct 31, 2004 Issued
Array ( [id] => 414729 [patent_doc_number] => 07284085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Managing configuration data in a flash configuration space in flash memory within a host interface port' [patent_app_type] => utility [patent_app_number] => 10/978801 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4240 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/284/07284085.pdf [firstpage_image] =>[orig_patent_app_number] => 10978801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/978801
Managing configuration data in a flash configuration space in flash memory within a host interface port Oct 31, 2004 Issued
Array ( [id] => 927388 [patent_doc_number] => 07318114 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-08 [patent_title] => 'System and method for dynamic memory interleaving and de-interleaving' [patent_app_type] => utility [patent_app_number] => 10/978249 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/318/07318114.pdf [firstpage_image] =>[orig_patent_app_number] => 10978249 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/978249
System and method for dynamic memory interleaving and de-interleaving Oct 28, 2004 Issued
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