Search

John A. Lane

Examiner (ID: 16902, Phone: (571)272-4208 , Office: P/2139 )

Most Active Art Unit
2139
Art Unit(s)
2309, 2139, 2185, 2188, 2751, 2189, 2186, 2305, 2303, 2312
Total Applications
2052
Issued Applications
1798
Pending Applications
47
Abandoned Applications
220

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1192451 [patent_doc_number] => 06735668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Process of using a DRAM with address control data' [patent_app_type] => B2 [patent_app_number] => 10/452619 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6535 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735668.pdf [firstpage_image] =>[orig_patent_app_number] => 10452619 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452619
Process of using a DRAM with address control data Jun 1, 2003 Issued
Array ( [id] => 7678266 [patent_doc_number] => 20030196070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Process of operating a DRAM system' [patent_app_type] => new [patent_app_number] => 10/452744 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6586 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20030196070.pdf [firstpage_image] =>[orig_patent_app_number] => 10452744 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452744
Process of operating a DRAM system Jun 1, 2003 Issued
Array ( [id] => 1196931 [patent_doc_number] => 06732226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Memory device for transferring streams of data' [patent_app_type] => B2 [patent_app_number] => 10/452618 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6535 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732226.pdf [firstpage_image] =>[orig_patent_app_number] => 10452618 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452618
Memory device for transferring streams of data Jun 1, 2003 Issued
Array ( [id] => 6810478 [patent_doc_number] => 20030200417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Process for controlling reading data from a DRAM array' [patent_app_type] => new [patent_app_number] => 10/452191 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6585 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200417.pdf [firstpage_image] =>[orig_patent_app_number] => 10452191 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452191
Process for controlling reading data from a DRAM array Jun 1, 2003 Issued
Array ( [id] => 1004648 [patent_doc_number] => 06910096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'SDRAM with command decoder coupled to address registers' [patent_app_type] => utility [patent_app_number] => 10/452339 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6543 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 553 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/910/06910096.pdf [firstpage_image] =>[orig_patent_app_number] => 10452339 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452339
SDRAM with command decoder coupled to address registers Jun 1, 2003 Issued
Array ( [id] => 7257980 [patent_doc_number] => 20040240459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Method and apparatus for avoiding collisions during packet enqueue and dequeue' [patent_app_type] => new [patent_app_number] => 10/448960 [patent_app_country] => US [patent_app_date] => 2003-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3343 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240459.pdf [firstpage_image] =>[orig_patent_app_number] => 10448960 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448960
Method and apparatus for avoiding collisions during packet enqueue and dequeue May 30, 2003 Issued
Array ( [id] => 6810442 [patent_doc_number] => 20030200381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Synchronous DRAM with control data buffer' [patent_app_type] => new [patent_app_number] => 10/449581 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6585 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200381.pdf [firstpage_image] =>[orig_patent_app_number] => 10449581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449581
Synchronous DRAM with control data buffer May 29, 2003 Issued
Array ( [id] => 7678302 [patent_doc_number] => 20030196034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Synchronous data system with control data buffer' [patent_app_type] => new [patent_app_number] => 10/449432 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6585 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20030196034.pdf [firstpage_image] =>[orig_patent_app_number] => 10449432 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449432
Synchronous data system with control data buffer May 29, 2003 Issued
Array ( [id] => 6726357 [patent_doc_number] => 20030208669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'System with control data buffer for transferring streams of data' [patent_app_type] => new [patent_app_number] => 10/449583 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6585 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20030208669.pdf [firstpage_image] =>[orig_patent_app_number] => 10449583 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449583
System with control data buffer for transferring streams of data May 29, 2003 Issued
Array ( [id] => 1200952 [patent_doc_number] => 06728829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Synchronous DRAM system with control data' [patent_app_type] => B2 [patent_app_number] => 10/448934 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6535 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728829.pdf [firstpage_image] =>[orig_patent_app_number] => 10448934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448934
Synchronous DRAM system with control data May 29, 2003 Issued
Array ( [id] => 7678270 [patent_doc_number] => 20030196066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'System and method for translation buffer accommodating multiple page sizes' [patent_app_type] => new [patent_app_number] => 10/446914 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10615 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20030196066.pdf [firstpage_image] =>[orig_patent_app_number] => 10446914 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/446914
System and method for translation buffer accommodating multiple page sizes May 26, 2003 Abandoned
Array ( [id] => 1200943 [patent_doc_number] => 06728828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Synchronous data transfer system' [patent_app_type] => B2 [patent_app_number] => 10/445134 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6552 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728828.pdf [firstpage_image] =>[orig_patent_app_number] => 10445134 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445134
Synchronous data transfer system May 22, 2003 Issued
Array ( [id] => 1161469 [patent_doc_number] => 06775746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors' [patent_app_type] => B2 [patent_app_number] => 10/435386 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6120 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775746.pdf [firstpage_image] =>[orig_patent_app_number] => 10435386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435386
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors May 11, 2003 Issued
Array ( [id] => 431339 [patent_doc_number] => 07269697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'Apparatus and methodology for an input port scheduler' [patent_app_type] => utility [patent_app_number] => 10/434001 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 19574 [patent_no_of_claims] => 92 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269697.pdf [firstpage_image] =>[orig_patent_app_number] => 10434001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/434001
Apparatus and methodology for an input port scheduler May 6, 2003 Issued
Array ( [id] => 914485 [patent_doc_number] => 07330927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-12 [patent_title] => 'Apparatus and methodology for a pointer manager' [patent_app_type] => utility [patent_app_number] => 10/431991 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 19555 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/330/07330927.pdf [firstpage_image] =>[orig_patent_app_number] => 10431991 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431991
Apparatus and methodology for a pointer manager May 6, 2003 Issued
Array ( [id] => 1229182 [patent_doc_number] => 06701414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'System and method for prefetching data into a cache based on miss distance' [patent_app_type] => B2 [patent_app_number] => 10/427908 [patent_app_country] => US [patent_app_date] => 2003-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5666 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701414.pdf [firstpage_image] =>[orig_patent_app_number] => 10427908 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/427908
System and method for prefetching data into a cache based on miss distance May 1, 2003 Issued
Array ( [id] => 1177602 [patent_doc_number] => 06760823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'File mapping system and related techniques' [patent_app_type] => B1 [patent_app_number] => 10/411500 [patent_app_country] => US [patent_app_date] => 2003-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 11992 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760823.pdf [firstpage_image] =>[orig_patent_app_number] => 10411500 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/411500
File mapping system and related techniques Apr 9, 2003 Issued
Array ( [id] => 6822905 [patent_doc_number] => 20030221066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Memory card and memory card data recording method' [patent_app_type] => new [patent_app_number] => 10/395219 [patent_app_country] => US [patent_app_date] => 2003-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7211 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20030221066.pdf [firstpage_image] =>[orig_patent_app_number] => 10395219 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/395219
Memory card and memory card data recording method Mar 24, 2003 Abandoned
Array ( [id] => 6728880 [patent_doc_number] => 20030185070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Memory control device' [patent_app_type] => new [patent_app_number] => 10/395386 [patent_app_country] => US [patent_app_date] => 2003-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7451 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20030185070.pdf [firstpage_image] =>[orig_patent_app_number] => 10395386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/395386
Memory control device for controlling transmission of data signals Mar 24, 2003 Issued
Array ( [id] => 7631554 [patent_doc_number] => 06665783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Memory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemes' [patent_app_type] => B2 [patent_app_number] => 10/379716 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4709 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665783.pdf [firstpage_image] =>[orig_patent_app_number] => 10379716 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379716
Memory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemes Mar 5, 2003 Issued
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