John A. Lane

Array ( [id] => 4118376 [patent_doc_number] => 06098161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method of generating address of coefficient memory in OFDM adaptive channel equalizer and apparatus employing the same' [patent_app_type] => 1 [patent_app_number] => 9/105247 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4774 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098161.pdf [firstpage_image] =>[orig_patent_app_number] => 105247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4238878 [patent_doc_number] => 06088762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Power failure mode for a memory controller' [patent_app_type] => 1 [patent_app_number] => 9/100229 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3092 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088762.pdf [firstpage_image] =>[orig_patent_app_number] => 100229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4208816 [patent_doc_number] => 06154814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Cache device that reduces waiting time necessary for a given subsequent request to gain access to the cache' [patent_app_type] => 1 [patent_app_number] => 9/097593 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4866 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154814.pdf [firstpage_image] =>[orig_patent_app_number] => 097593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4118180 [patent_doc_number] => 06098147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Longest coincidence data detection using associative memory units having interleaved data' [patent_app_type] => 1 [patent_app_number] => 9/097598 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 3921 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098147.pdf [firstpage_image] =>[orig_patent_app_number] => 097598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4277440 [patent_doc_number] => 06179492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method of and apparatus for duplicating, upgrading and configuring hard disk drives' [patent_app_type] => 1 [patent_app_number] => 9/097558 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3720 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/179/06179492.pdf [firstpage_image] =>[orig_patent_app_number] => 097558 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4256447 [patent_doc_number] => 06144983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method and apparatus for dynamic lock granularity escalation and de-escalation in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/094214 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8432 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144983.pdf [firstpage_image] =>[orig_patent_app_number] => 094214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152357 [patent_doc_number] => 06148362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Microcomputer using nonvolatile semiconductor memory to store user code/data' [patent_app_type] => 1 [patent_app_number] => 9/081634 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3876 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148362.pdf [firstpage_image] =>[orig_patent_app_number] => 081634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1538806 [patent_doc_number] => 06411984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Processor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/071718 [patent_app_country] => US [patent_app_date] => 1998-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 63 [patent_no_of_words] => 26552 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411984.pdf [firstpage_image] =>[orig_patent_app_number] => 09071718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4138718 [patent_doc_number] => 06073210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Synchronization of weakly ordered write combining operations using a fencing mechanism' [patent_app_type] => 1 [patent_app_number] => 9/053377 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7159 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073210.pdf [firstpage_image] =>[orig_patent_app_number] => 053377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4177237 [patent_doc_number] => 06105111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method and apparatus for providing a cache management technique' [patent_app_type] => 1 [patent_app_number] => 9/053527 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105111.pdf [firstpage_image] =>[orig_patent_app_number] => 053527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4156001 [patent_doc_number] => 06122715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method and system for optimizing write combining performance in a shared buffer structure' [patent_app_type] => 1 [patent_app_number] => 9/053384 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7245 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122715.pdf [firstpage_image] =>[orig_patent_app_number] => 053384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237268 [patent_doc_number] => 06112279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Virtual web caching system' [patent_app_type] => 1 [patent_app_number] => 9/052284 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4269 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112279.pdf [firstpage_image] =>[orig_patent_app_number] => 052284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250858 [patent_doc_number] => 06081475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Write control apparatus for memory devices' [patent_app_type] => 1 [patent_app_number] => 9/021719 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5650 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081475.pdf [firstpage_image] =>[orig_patent_app_number] => 021719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4138883 [patent_doc_number] => 06073221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Synchronization of shared data stores through use of non-empty track copy procedure' [patent_app_type] => 1 [patent_app_number] => 9/002851 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1814 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073221.pdf [firstpage_image] =>[orig_patent_app_number] => 002851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4153212 [patent_doc_number] => 06061293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Synchronous interface to a self-timed memory array' [patent_app_type] => 1 [patent_app_number] => 9/002094 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3025 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061293.pdf [firstpage_image] =>[orig_patent_app_number] => 002094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4223964 [patent_doc_number] => 06079000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'XPC backup for in-process audit' [patent_app_type] => 1 [patent_app_number] => 9/001136 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9701 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079000.pdf [firstpage_image] =>[orig_patent_app_number] => 001136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4088734 [patent_doc_number] => 06070230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Multi-threaded read ahead prediction by pattern recognition' [patent_app_type] => 1 [patent_app_number] => 8/999027 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6076 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070230.pdf [firstpage_image] =>[orig_patent_app_number] => 999027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4292166 [patent_doc_number] => 06247094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Cache memory architecture with on-chip tag array and off-chip data array' [patent_app_type] => 1 [patent_app_number] => 8/996110 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6458 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247094.pdf [firstpage_image] =>[orig_patent_app_number] => 996110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4118330 [patent_doc_number] => 06098158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Software-enabled fast boot' [patent_app_type] => 1 [patent_app_number] => 8/993518 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3370 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098158.pdf [firstpage_image] =>[orig_patent_app_number] => 993518 [rel_patent_id] =>[rel_patent_doc_number] =>)