Search

John A. Lane

Examiner (ID: 16902, Phone: (571)272-4208 , Office: P/2139 )

Most Active Art Unit
2139
Art Unit(s)
2309, 2139, 2185, 2188, 2751, 2189, 2186, 2305, 2303, 2312
Total Applications
2052
Issued Applications
1798
Pending Applications
47
Abandoned Applications
220

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4177600 [patent_doc_number] => 06108746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Semiconductor memory having an arithmetic function and a terminal arrangement for coordinating operation with a higher processor' [patent_app_type] => 1 [patent_app_number] => 8/945575 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108746.pdf [firstpage_image] =>[orig_patent_app_number] => 945575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/945575
Semiconductor memory having an arithmetic function and a terminal arrangement for coordinating operation with a higher processor Oct 30, 1997 Issued
Array ( [id] => 4177849 [patent_doc_number] => 06108762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Address processor and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/959325 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2748 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108762.pdf [firstpage_image] =>[orig_patent_app_number] => 959325 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959325
Address processor and method therefor Oct 27, 1997 Issued
Array ( [id] => 4100877 [patent_doc_number] => 06018786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Trace based instruction caching' [patent_app_type] => 1 [patent_app_number] => 8/956375 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7927 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018786.pdf [firstpage_image] =>[orig_patent_app_number] => 956375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956375
Trace based instruction caching Oct 22, 1997 Issued
Array ( [id] => 3806060 [patent_doc_number] => 05822785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Data transfer using local and global address translation and authorization' [patent_app_type] => 1 [patent_app_number] => 8/951295 [patent_app_country] => US [patent_app_date] => 1997-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 7509 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822785.pdf [firstpage_image] =>[orig_patent_app_number] => 951295 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/951295
Data transfer using local and global address translation and authorization Oct 15, 1997 Issued
Array ( [id] => 4026701 [patent_doc_number] => 05890188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Nonvolatile semiconductor memory device having means for selective transfer of memory block contents and for chaining together unused memory blocks' [patent_app_type] => 1 [patent_app_number] => 8/948089 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 38 [patent_no_of_words] => 8186 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890188.pdf [firstpage_image] =>[orig_patent_app_number] => 948089 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/948089
Nonvolatile semiconductor memory device having means for selective transfer of memory block contents and for chaining together unused memory blocks Oct 8, 1997 Issued
Array ( [id] => 4346186 [patent_doc_number] => 06333873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Semiconductor memory device with an internal voltage generating circuit' [patent_app_type] => 1 [patent_app_number] => 8/942692 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 73 [patent_no_of_words] => 30958 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333873.pdf [firstpage_image] =>[orig_patent_app_number] => 942692 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942692
Semiconductor memory device with an internal voltage generating circuit Sep 28, 1997 Issued
Array ( [id] => 1587433 [patent_doc_number] => 06425061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Apparatuses for exchanging information over computer and broadcast networks' [patent_app_type] => B1 [patent_app_number] => 08/940199 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10963 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425061.pdf [firstpage_image] =>[orig_patent_app_number] => 08940199 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940199
Apparatuses for exchanging information over computer and broadcast networks Sep 28, 1997 Issued
Array ( [id] => 4211248 [patent_doc_number] => 06044434 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Circular buffer for processing audio samples' [patent_app_type] => 1 [patent_app_number] => 8/937140 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2521 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044434.pdf [firstpage_image] =>[orig_patent_app_number] => 937140 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937140
Circular buffer for processing audio samples Sep 23, 1997 Issued
Array ( [id] => 4010902 [patent_doc_number] => 05859515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method of operating a virtual mechanical module which simulates a mechanical device' [patent_app_type] => 1 [patent_app_number] => 8/934108 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 142 [patent_no_of_words] => 32543 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859515.pdf [firstpage_image] =>[orig_patent_app_number] => 934108 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934108
Method of operating a virtual mechanical module which simulates a mechanical device Sep 18, 1997 Issued
Array ( [id] => 4262306 [patent_doc_number] => 06137767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Optical disk memory content display apparatus, system and display control method' [patent_app_type] => 1 [patent_app_number] => 8/928486 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3602 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137767.pdf [firstpage_image] =>[orig_patent_app_number] => 928486 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/928486
Optical disk memory content display apparatus, system and display control method Sep 11, 1997 Issued
Array ( [id] => 4099882 [patent_doc_number] => 06055606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Writeback cache cell with a dual ported dirty bit cell and method for operating such a cache cell' [patent_app_type] => 1 [patent_app_number] => 8/924604 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3687 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055606.pdf [firstpage_image] =>[orig_patent_app_number] => 924604 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924604
Writeback cache cell with a dual ported dirty bit cell and method for operating such a cache cell Sep 4, 1997 Issued
Array ( [id] => 3973341 [patent_doc_number] => 05978885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method and apparatus for self-timing associative data memory' [patent_app_type] => 1 [patent_app_number] => 8/920395 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5928 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978885.pdf [firstpage_image] =>[orig_patent_app_number] => 920395 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920395
Method and apparatus for self-timing associative data memory Aug 28, 1997 Issued
Array ( [id] => 4114519 [patent_doc_number] => 06049853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Data replication across nodes of a multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 8/920477 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049853.pdf [firstpage_image] =>[orig_patent_app_number] => 920477 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920477
Data replication across nodes of a multiprocessor computer system Aug 28, 1997 Issued
Array ( [id] => 3973625 [patent_doc_number] => 05978903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Apparatus and method for automatically accessing a dynamic RAM for system management interrupt handling' [patent_app_type] => 1 [patent_app_number] => 8/914511 [patent_app_country] => US [patent_app_date] => 1997-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5472 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978903.pdf [firstpage_image] =>[orig_patent_app_number] => 914511 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/914511
Apparatus and method for automatically accessing a dynamic RAM for system management interrupt handling Aug 18, 1997 Issued
Array ( [id] => 4257785 [patent_doc_number] => 06145070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method for digital signal processing, DSP, mobile communication and audio-device' [patent_app_type] => 1 [patent_app_number] => 8/912243 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5327 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145070.pdf [firstpage_image] =>[orig_patent_app_number] => 912243 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/912243
Method for digital signal processing, DSP, mobile communication and audio-device Aug 14, 1997 Issued
Array ( [id] => 3971270 [patent_doc_number] => 06000023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method for partitioning storage regions on hard disk and computer system adapted to the same' [patent_app_type] => 1 [patent_app_number] => 8/897252 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3812 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000023.pdf [firstpage_image] =>[orig_patent_app_number] => 897252 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/897252
Method for partitioning storage regions on hard disk and computer system adapted to the same Jul 17, 1997 Issued
Array ( [id] => 4044823 [patent_doc_number] => 05903911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Cache-based computer system employing memory control circuit and method for write allocation and data prefetch' [patent_app_type] => 1 [patent_app_number] => 8/903232 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7090 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903911.pdf [firstpage_image] =>[orig_patent_app_number] => 903232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903232
Cache-based computer system employing memory control circuit and method for write allocation and data prefetch Jul 17, 1997 Issued
Array ( [id] => 4162186 [patent_doc_number] => 06032220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Memory device with dual timing and signal latching control' [patent_app_type] => 1 [patent_app_number] => 8/896405 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6801 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032220.pdf [firstpage_image] =>[orig_patent_app_number] => 896405 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896405
Memory device with dual timing and signal latching control Jul 17, 1997 Issued
Array ( [id] => 4012530 [patent_doc_number] => 05986965 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method and device for writing data in non-volatile memory circuit' [patent_app_type] => 1 [patent_app_number] => 8/896985 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2688 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986965.pdf [firstpage_image] =>[orig_patent_app_number] => 896985 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896985
Method and device for writing data in non-volatile memory circuit Jul 17, 1997 Issued
Array ( [id] => 3954782 [patent_doc_number] => 05873128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Data processing system with dynamic address translation function' [patent_app_type] => 1 [patent_app_number] => 8/890345 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2338 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/873/05873128.pdf [firstpage_image] =>[orig_patent_app_number] => 890345 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890345
Data processing system with dynamic address translation function Jul 8, 1997 Issued
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