Search

John A. Lane

Examiner (ID: 16902, Phone: (571)272-4208 , Office: P/2139 )

Most Active Art Unit
2139
Art Unit(s)
2309, 2139, 2185, 2188, 2751, 2189, 2186, 2305, 2303, 2312
Total Applications
2052
Issued Applications
1798
Pending Applications
47
Abandoned Applications
220

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3759127 [patent_doc_number] => 05787494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Software assisted hardware TLB miss handler' [patent_app_type] => 1 [patent_app_number] => 8/532948 [patent_app_country] => US [patent_app_date] => 1995-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6934 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787494.pdf [firstpage_image] =>[orig_patent_app_number] => 532948 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/532948
Software assisted hardware TLB miss handler Sep 21, 1995 Issued
Array ( [id] => 3575834 [patent_doc_number] => 05526505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Fast lookahead circuit to identify an item in a large binary set' [patent_app_type] => 1 [patent_app_number] => 8/493597 [patent_app_country] => US [patent_app_date] => 1995-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4461 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526505.pdf [firstpage_image] =>[orig_patent_app_number] => 493597 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/493597
Fast lookahead circuit to identify an item in a large binary set Jun 21, 1995 Issued
Array ( [id] => 3507363 [patent_doc_number] => 05509131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'System for pointer updating across paged memory' [patent_app_type] => 1 [patent_app_number] => 8/493058 [patent_app_country] => US [patent_app_date] => 1995-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 16825 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/509/05509131.pdf [firstpage_image] =>[orig_patent_app_number] => 493058 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/493058
System for pointer updating across paged memory Jun 20, 1995 Issued
Array ( [id] => 3601610 [patent_doc_number] => 05568442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'RISC processor having improved instruction fetching capability and utilizing address bit predecoding for a segmented cache memory' [patent_app_type] => 1 [patent_app_number] => 8/491491 [patent_app_country] => US [patent_app_date] => 1995-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1882 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 436 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568442.pdf [firstpage_image] =>[orig_patent_app_number] => 491491 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/491491
RISC processor having improved instruction fetching capability and utilizing address bit predecoding for a segmented cache memory Jun 15, 1995 Issued
Array ( [id] => 3848149 [patent_doc_number] => 05740402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Conflict resolution in interleaved memory systems with multiple parallel accesses' [patent_app_type] => 1 [patent_app_number] => 8/487240 [patent_app_country] => US [patent_app_date] => 1995-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3493 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740402.pdf [firstpage_image] =>[orig_patent_app_number] => 487240 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/487240
Conflict resolution in interleaved memory systems with multiple parallel accesses Jun 12, 1995 Issued
Array ( [id] => 3743758 [patent_doc_number] => 05636335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Graphics computer system having a second palette shadowing data in a first palette' [patent_app_type] => 1 [patent_app_number] => 8/479478 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 86 [patent_no_of_words] => 35444 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636335.pdf [firstpage_image] =>[orig_patent_app_number] => 479478 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/479478
Graphics computer system having a second palette shadowing data in a first palette Jun 6, 1995 Issued
Array ( [id] => 3700189 [patent_doc_number] => 05696924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Memory access circuit with address translation performing auto increment of translated address on writes and return to translated address on reads' [patent_app_type] => 1 [patent_app_number] => 8/487750 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 89 [patent_no_of_words] => 35339 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696924.pdf [firstpage_image] =>[orig_patent_app_number] => 487750 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/487750
Memory access circuit with address translation performing auto increment of translated address on writes and return to translated address on reads Jun 6, 1995 Issued
Array ( [id] => 3519166 [patent_doc_number] => 05587962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Memory circuit accommodating both serial and random access including an alternate address buffer register' [patent_app_type] => 1 [patent_app_number] => 8/483003 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6188 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587962.pdf [firstpage_image] =>[orig_patent_app_number] => 483003 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/483003
Memory circuit accommodating both serial and random access including an alternate address buffer register Jun 6, 1995 Issued
Array ( [id] => 4323907 [patent_doc_number] => 06189077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Two computer access circuit using address translation into common register file' [patent_app_type] => 1 [patent_app_number] => 8/476786 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 87 [patent_no_of_words] => 35549 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189077.pdf [firstpage_image] =>[orig_patent_app_number] => 476786 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/476786
Two computer access circuit using address translation into common register file Jun 6, 1995 Issued
08/482706 A CIRCUIT AND METHOD FOR TWO STAGE REDUNDANCY DECODING Jun 6, 1995 Abandoned
Array ( [id] => 1499261 [patent_doc_number] => 06404691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Semiconductor memory device for simple cache system' [patent_app_type] => B1 [patent_app_number] => 08/472770 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9333 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404691.pdf [firstpage_image] =>[orig_patent_app_number] => 08472770 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472770
Semiconductor memory device for simple cache system Jun 6, 1995 Issued
Array ( [id] => 4317266 [patent_doc_number] => 06188635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Process of synchronously writing data to a dynamic random access memory array' [patent_app_type] => 1 [patent_app_number] => 8/488231 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6160 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188635.pdf [firstpage_image] =>[orig_patent_app_number] => 488231 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/488231
Process of synchronously writing data to a dynamic random access memory array Jun 6, 1995 Issued
08/465908 INFORMATION RECORDING DEVICE AND INFORMATION RECORDING AND REPRODUCING PROCESS Jun 5, 1995 Abandoned
Array ( [id] => 3971074 [patent_doc_number] => 05901093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Redundancy architecture and method for block write access cycles permitting defective memory line replacement' [patent_app_type] => 1 [patent_app_number] => 8/464044 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5674 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901093.pdf [firstpage_image] =>[orig_patent_app_number] => 464044 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/464044
Redundancy architecture and method for block write access cycles permitting defective memory line replacement Jun 4, 1995 Issued
Array ( [id] => 3738342 [patent_doc_number] => 05652853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Multi-zone relocation facility computer memory system' [patent_app_type] => 1 [patent_app_number] => 8/455818 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5428 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652853.pdf [firstpage_image] =>[orig_patent_app_number] => 455818 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/455818
Multi-zone relocation facility computer memory system May 30, 1995 Issued
Array ( [id] => 3673326 [patent_doc_number] => 05649159 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Data processor with a multi-level protection mechanism, multi-level protection circuit, and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/445817 [patent_app_country] => US [patent_app_date] => 1995-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 16950 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649159.pdf [firstpage_image] =>[orig_patent_app_number] => 445817 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/445817
Data processor with a multi-level protection mechanism, multi-level protection circuit, and method therefor May 21, 1995 Issued
Array ( [id] => 4171574 [patent_doc_number] => 06125433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method of accomplishing a least-recently-used replacement scheme using ripple counters' [patent_app_type] => 1 [patent_app_number] => 8/442726 [patent_app_country] => US [patent_app_date] => 1995-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 8332 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125433.pdf [firstpage_image] =>[orig_patent_app_number] => 442726 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/442726
Method of accomplishing a least-recently-used replacement scheme using ripple counters May 16, 1995 Issued
Array ( [id] => 3760666 [patent_doc_number] => 05717898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Cache coherency mechanism for multiprocessor computer systems' [patent_app_type] => 1 [patent_app_number] => 8/438615 [patent_app_country] => US [patent_app_date] => 1995-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 8578 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717898.pdf [firstpage_image] =>[orig_patent_app_number] => 438615 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/438615
Cache coherency mechanism for multiprocessor computer systems May 9, 1995 Issued
Array ( [id] => 3642301 [patent_doc_number] => 05687354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Memory system and method for protecting the contents of a ROM type memory' [patent_app_type] => 1 [patent_app_number] => 8/427460 [patent_app_country] => US [patent_app_date] => 1995-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4348 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687354.pdf [firstpage_image] =>[orig_patent_app_number] => 427460 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/427460
Memory system and method for protecting the contents of a ROM type memory Apr 23, 1995 Issued
Array ( [id] => 3867660 [patent_doc_number] => 05706232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Semiconductor memory with multiple clocking for test mode entry' [patent_app_type] => 1 [patent_app_number] => 8/424722 [patent_app_country] => US [patent_app_date] => 1995-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 23708 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706232.pdf [firstpage_image] =>[orig_patent_app_number] => 424722 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/424722
Semiconductor memory with multiple clocking for test mode entry Apr 17, 1995 Issued
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