John A. Mcpherson

Array ( [id] => 2985267 [patent_doc_number] => 05208773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-04 [patent_title] => 'Semiconductor memory device having bit lines and word lines different in data reading and data writing' [patent_app_type] => 1 [patent_app_number] => 7/669437 [patent_app_country] => US [patent_app_date] => 1991-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 12140 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/208/05208773.pdf [firstpage_image] =>[orig_patent_app_number] => 669437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2904121 [patent_doc_number] => 05177706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-05 [patent_title] => 'Semiconductor memory device having a plurality of ports' [patent_app_type] => 1 [patent_app_number] => 7/666518 [patent_app_country] => US [patent_app_date] => 1991-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 36 [patent_no_of_words] => 7334 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/177/05177706.pdf [firstpage_image] =>[orig_patent_app_number] => 666518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2977750 [patent_doc_number] => 05202851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Word line driving circuit' [patent_app_type] => 1 [patent_app_number] => 7/665698 [patent_app_country] => US [patent_app_date] => 1991-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1595 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202851.pdf [firstpage_image] =>[orig_patent_app_number] => 665698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2830473 [patent_doc_number] => 05168466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-01 [patent_title] => 'Bias current generator circuit for a sense amplifier' [patent_app_type] => 1 [patent_app_number] => 7/664147 [patent_app_country] => US [patent_app_date] => 1991-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3170 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/168/05168466.pdf [firstpage_image] =>[orig_patent_app_number] => 664147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2880032 [patent_doc_number] => 05153856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-06 [patent_title] => 'DRAM controller' [patent_app_type] => 1 [patent_app_number] => 7/660225 [patent_app_country] => US [patent_app_date] => 1991-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3929 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/153/05153856.pdf [firstpage_image] =>[orig_patent_app_number] => 660225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2800884 [patent_doc_number] => 05103423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-07 [patent_title] => 'Dynamic random access memory and a method of operating the same' [patent_app_type] => 1 [patent_app_number] => 7/657778 [patent_app_country] => US [patent_app_date] => 1991-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10936 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/103/05103423.pdf [firstpage_image] =>[orig_patent_app_number] => 657778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2885861 [patent_doc_number] => 05185718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Memory array architecture for flash memory' [patent_app_type] => 1 [patent_app_number] => 7/658279 [patent_app_country] => US [patent_app_date] => 1991-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5490 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185718.pdf [firstpage_image] =>[orig_patent_app_number] => 658279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2911607 [patent_doc_number] => 05218569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-08 [patent_title] => 'Electrically alterable non-volatile memory with n-bits per memory cell' [patent_app_type] => 1 [patent_app_number] => 7/652878 [patent_app_country] => US [patent_app_date] => 1991-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7248 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/218/05218569.pdf [firstpage_image] =>[orig_patent_app_number] => 652878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2986148 [patent_doc_number] => 05226009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Semiconductor memory device supporting cache and method of driving the same' [patent_app_type] => 1 [patent_app_number] => 7/651848 [patent_app_country] => US [patent_app_date] => 1991-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 14860 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226009.pdf [firstpage_image] =>[orig_patent_app_number] => 651848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2944638 [patent_doc_number] => 05197029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Common-line connection for integrated memory array' [patent_app_type] => 1 [patent_app_number] => 7/651817 [patent_app_country] => US [patent_app_date] => 1991-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3149 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197029.pdf [firstpage_image] =>[orig_patent_app_number] => 651817 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3086746 [patent_doc_number] => 05297098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Control apparatus for data storage apparatus' [patent_app_type] => 1 [patent_app_number] => 7/650418 [patent_app_country] => US [patent_app_date] => 1991-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4040 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297098.pdf [firstpage_image] =>[orig_patent_app_number] => 650418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2815483 [patent_doc_number] => 05148392 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/649499 [patent_app_country] => US [patent_app_date] => 1991-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3772 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148392.pdf [firstpage_image] =>[orig_patent_app_number] => 649499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2899495 [patent_doc_number] => 05239512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'Method and apparatus for blockwise storage of pictures having variable aspect ratios' [patent_app_type] => 1 [patent_app_number] => 7/649518 [patent_app_country] => US [patent_app_date] => 1991-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7196 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/239/05239512.pdf [firstpage_image] =>[orig_patent_app_number] => 649518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3061926 [patent_doc_number] => 05307318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Semiconductor integrated circuit device having main power terminal and backup power terminal independently of each other' [patent_app_type] => 1 [patent_app_number] => 7/657768 [patent_app_country] => US [patent_app_date] => 1991-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3889 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/307/05307318.pdf [firstpage_image] =>[orig_patent_app_number] => 657768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2986185 [patent_doc_number] => 05226011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Static type RAM' [patent_app_type] => 1 [patent_app_number] => 7/646907 [patent_app_country] => US [patent_app_date] => 1991-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226011.pdf [firstpage_image] =>[orig_patent_app_number] => 646907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2944603 [patent_doc_number] => 05197027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Single transistor EEPROM architecture' [patent_app_type] => 1 [patent_app_number] => 7/645507 [patent_app_country] => US [patent_app_date] => 1991-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4350 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197027.pdf [firstpage_image] =>[orig_patent_app_number] => 645507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2742406 [patent_doc_number] => 05040151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-13 [patent_title] => 'Memory circuit with improved power interconnections' [patent_app_type] => 1 [patent_app_number] => 7/644988 [patent_app_country] => US [patent_app_date] => 1991-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3043 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/040/05040151.pdf [firstpage_image] =>[orig_patent_app_number] => 644988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2815629 [patent_doc_number] => 05148400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Semiconductor memory circuit having an improved restoring control circuit' [patent_app_type] => 1 [patent_app_number] => 7/644865 [patent_app_country] => US [patent_app_date] => 1991-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4506 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148400.pdf [firstpage_image] =>[orig_patent_app_number] => 644865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2964113 [patent_doc_number] => 05231604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-27 [patent_title] => 'Semiconductor memory device having column redundancy system' [patent_app_type] => 1 [patent_app_number] => 7/643127 [patent_app_country] => US [patent_app_date] => 1991-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5642 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/231/05231604.pdf [firstpage_image] =>[orig_patent_app_number] => 643127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2830449 [patent_doc_number] => 05168465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-01 [patent_title] => 'Highly compact EPROM and flash EEPROM devices' [patent_app_type] => 1 [patent_app_number] => 7/641508 [patent_app_country] => US [patent_app_date] => 1991-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 48 [patent_no_of_words] => 19551 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/168/05168465.pdf [firstpage_image] =>[orig_patent_app_number] => 641508 [rel_patent_id] =>[rel_patent_doc_number] =>)