Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3842669
[patent_doc_number] => 05784650
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'System for increasing multimedia performance and other real time applications by including a local expansion bus and a multimedia bus on the computer system motherboard'
[patent_app_type] => 1
[patent_app_number] => 8/526769
[patent_app_country] => US
[patent_app_date] => 1995-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6438
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/784/05784650.pdf
[firstpage_image] =>[orig_patent_app_number] => 526769
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/526769 | System for increasing multimedia performance and other real time applications by including a local expansion bus and a multimedia bus on the computer system motherboard | Sep 10, 1995 | Issued |
Array
(
[id] => 3797462
[patent_doc_number] => 05819112
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Apparatus for controlling an I/O port by queuing requests and in response to a predefined condition, enabling the I/O port to receive the interrupt requests'
[patent_app_type] => 1
[patent_app_number] => 8/525464
[patent_app_country] => US
[patent_app_date] => 1995-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 12216
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/819/05819112.pdf
[firstpage_image] =>[orig_patent_app_number] => 525464
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/525464 | Apparatus for controlling an I/O port by queuing requests and in response to a predefined condition, enabling the I/O port to receive the interrupt requests | Sep 7, 1995 | Issued |
08/511916 | I/O DECODER MAP | Aug 6, 1995 | Abandoned |
Array
(
[id] => 3847682
[patent_doc_number] => 05740374
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'System for transferring messages via different sub-networks by converting control codes into reference code compatible with a reference protocol and encapsulating the code with the message'
[patent_app_type] => 1
[patent_app_number] => 8/498907
[patent_app_country] => US
[patent_app_date] => 1995-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2775
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/740/05740374.pdf
[firstpage_image] =>[orig_patent_app_number] => 498907
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/498907 | System for transferring messages via different sub-networks by converting control codes into reference code compatible with a reference protocol and encapsulating the code with the message | Jul 5, 1995 | Issued |
Array
(
[id] => 3842585
[patent_doc_number] => 05784645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Apparatus having a first microcomputer for reading first and second data from a non-volatile memory and processing the second data and transferring the first and second microcomputer'
[patent_app_type] => 1
[patent_app_number] => 8/497250
[patent_app_country] => US
[patent_app_date] => 1995-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 3896
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/784/05784645.pdf
[firstpage_image] =>[orig_patent_app_number] => 497250
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/497250 | Apparatus having a first microcomputer for reading first and second data from a non-volatile memory and processing the second data and transferring the first and second microcomputer | Jun 29, 1995 | Issued |
Array
(
[id] => 3895433
[patent_doc_number] => 05765026
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Method for implementing state machine using link lists by dividing each one of the combinations into an initial section, an immediate section, and a final section'
[patent_app_type] => 1
[patent_app_number] => 8/491460
[patent_app_country] => US
[patent_app_date] => 1995-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4295
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/765/05765026.pdf
[firstpage_image] =>[orig_patent_app_number] => 491460
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/491460 | Method for implementing state machine using link lists by dividing each one of the combinations into an initial section, an immediate section, and a final section | Jun 15, 1995 | Issued |
Array
(
[id] => 3785574
[patent_doc_number] => 05734927
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-31
[patent_title] => 'System having registers for receiving data, registers for transmitting data, both at a different clock rate, and control circuitry for shifting the different clock rates'
[patent_app_type] => 1
[patent_app_number] => 8/489463
[patent_app_country] => US
[patent_app_date] => 1995-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 40
[patent_no_of_words] => 32412
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/734/05734927.pdf
[firstpage_image] =>[orig_patent_app_number] => 489463
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/489463 | System having registers for receiving data, registers for transmitting data, both at a different clock rate, and control circuitry for shifting the different clock rates | Jun 7, 1995 | Issued |
Array
(
[id] => 3859512
[patent_doc_number] => 05745793
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Apparatus having a circular buffer that maintains a one entry gap between elements written to the microprocessor and elements operated on by the clock'
[patent_app_type] => 1
[patent_app_number] => 8/485965
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 24
[patent_no_of_words] => 6461
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/745/05745793.pdf
[firstpage_image] =>[orig_patent_app_number] => 485965
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/485965 | Apparatus having a circular buffer that maintains a one entry gap between elements written to the microprocessor and elements operated on by the clock | Jun 6, 1995 | Issued |
08/473110 | BUS ANALYZER FOR CAPTURING BUS SIGNALS AT A PREDETERMINED RATE AND UPON ASSERTION OF A DATA VALID SIGNAL | Jun 6, 1995 | Abandoned |
Array
(
[id] => 3899289
[patent_doc_number] => 05748983
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Computer system having a dedicated multimedia engine and multimedia memory having arbitration logic which grants main memory access to either the CPU or multimedia engine'
[patent_app_type] => 1
[patent_app_number] => 8/474554
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4291
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748983.pdf
[firstpage_image] =>[orig_patent_app_number] => 474554
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/474554 | Computer system having a dedicated multimedia engine and multimedia memory having arbitration logic which grants main memory access to either the CPU or multimedia engine | Jun 6, 1995 | Issued |
Array
(
[id] => 3702238
[patent_doc_number] => 05692219
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-25
[patent_title] => 'System and method for disabling or re-enabling PCI-compliant devices in a computer system by masking the idsel signal with a disable or re-enable signal'
[patent_app_type] => 1
[patent_app_number] => 8/485056
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1896
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/692/05692219.pdf
[firstpage_image] =>[orig_patent_app_number] => 485056
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/485056 | System and method for disabling or re-enabling PCI-compliant devices in a computer system by masking the idsel signal with a disable or re-enable signal | Jun 6, 1995 | Issued |
Array
(
[id] => 3634518
[patent_doc_number] => 05689689
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-18
[patent_title] => 'Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator producing a clock signal synchronous with a master clock signal'
[patent_app_type] => 1
[patent_app_number] => 8/483748
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 56
[patent_no_of_words] => 61713
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/689/05689689.pdf
[firstpage_image] =>[orig_patent_app_number] => 483748
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/483748 | Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator producing a clock signal synchronous with a master clock signal | Jun 6, 1995 | Issued |
08/488316 | INFORMATION HANDLING SYSTEM INCLUDING OPTIMIZED DATA BLOCK TRANSFER | Jun 6, 1995 | Abandoned |
Array
(
[id] => 3813785
[patent_doc_number] => 05828898
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Microcomputer for outputting data to the outside of the microcomputer in real time in response to a RTP output request signal received from outside the microcomputer'
[patent_app_type] => 1
[patent_app_number] => 8/470650
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 1334
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/828/05828898.pdf
[firstpage_image] =>[orig_patent_app_number] => 470650
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/470650 | Microcomputer for outputting data to the outside of the microcomputer in real time in response to a RTP output request signal received from outside the microcomputer | Jun 5, 1995 | Issued |
Array
(
[id] => 3700147
[patent_doc_number] => 05664073
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Control system for transportation ticket printer having plurality of dual process personal computer boards for performing general computing tasks and sending data to printer control module'
[patent_app_type] => 1
[patent_app_number] => 8/470919
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 28
[patent_no_of_words] => 11138
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/664/05664073.pdf
[firstpage_image] =>[orig_patent_app_number] => 470919
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/470919 | Control system for transportation ticket printer having plurality of dual process personal computer boards for performing general computing tasks and sending data to printer control module | Jun 5, 1995 | Issued |
Array
(
[id] => 3746046
[patent_doc_number] => 05694618
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Apparatus which transmits a check signal to determine whether a printer is capable of bidirectional data transmission and remotely setting the printer operating environment accordingly'
[patent_app_type] => 1
[patent_app_number] => 8/461929
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 3945
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/694/05694618.pdf
[firstpage_image] =>[orig_patent_app_number] => 461929
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/461929 | Apparatus which transmits a check signal to determine whether a printer is capable of bidirectional data transmission and remotely setting the printer operating environment accordingly | Jun 4, 1995 | Issued |
08/455561 | GRAPHICS AND SOUND STORAGE AND PLAYBACK IN SMALL A FORMFACTOR DEVICE | May 30, 1995 | Abandoned |
Array
(
[id] => 3701333
[patent_doc_number] => 05696994
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Serial interface having control circuits for enabling or disabling N-channel or P-channel transistors to allow for operation in two different transfer modes'
[patent_app_type] => 1
[patent_app_number] => 8/451965
[patent_app_country] => US
[patent_app_date] => 1995-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 29
[patent_no_of_words] => 9604
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696994.pdf
[firstpage_image] =>[orig_patent_app_number] => 451965
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/451965 | Serial interface having control circuits for enabling or disabling N-channel or P-channel transistors to allow for operation in two different transfer modes | May 25, 1995 | Issued |
Array
(
[id] => 3898521
[patent_doc_number] => 05805923
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Configurable power management system having a clock stabilization filter that can be enabled or bypassed depending upon whether a crystal or can oscillator is used'
[patent_app_type] => 1
[patent_app_number] => 8/451206
[patent_app_country] => US
[patent_app_date] => 1995-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 7508
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/805/05805923.pdf
[firstpage_image] =>[orig_patent_app_number] => 451206
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/451206 | Configurable power management system having a clock stabilization filter that can be enabled or bypassed depending upon whether a crystal or can oscillator is used | May 25, 1995 | Issued |
Array
(
[id] => 3844572
[patent_doc_number] => 05713027
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-27
[patent_title] => 'Method and apparatus for controlling the shutdown of computer systems by using service utilization information and examining a dependency relationship between the computers'
[patent_app_type] => 1
[patent_app_number] => 8/450119
[patent_app_country] => US
[patent_app_date] => 1995-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 11433
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/713/05713027.pdf
[firstpage_image] =>[orig_patent_app_number] => 450119
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/450119 | Method and apparatus for controlling the shutdown of computer systems by using service utilization information and examining a dependency relationship between the computers | May 24, 1995 | Issued |