John B Sotomayor
Examiner (ID: 832, Phone: (571)272-6978 , Office: P/3646 )
Most Active Art Unit | 3662 |
Art Unit(s) | 3662, 3642, 2202, 3646, 2201, 3641 |
Total Applications | 2701 |
Issued Applications | 2479 |
Pending Applications | 70 |
Abandoned Applications | 152 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16470332
[patent_doc_number] => 20200371869
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-26
[patent_title] => SEMICONDUCTOR MEMORY DEVICES, AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/682685
[patent_app_country] => US
[patent_app_date] => 2019-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682685
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/682685 | Semiconductor memory devices, and methods of operating semiconductor memory devices | Nov 12, 2019 | Issued |
Array
(
[id] => 15627017
[patent_doc_number] => 20200083913
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-12
[patent_title] => RATE MATCHING METHODS FOR LDPC CODES
[patent_app_type] => utility
[patent_app_number] => 16/680774
[patent_app_country] => US
[patent_app_date] => 2019-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12117
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680774
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/680774 | Rate matching methods for LDPC codes | Nov 11, 2019 | Issued |
Array
(
[id] => 16789875
[patent_doc_number] => 10992318
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-27
[patent_title] => Coding method and apparatus, and device
[patent_app_type] => utility
[patent_app_number] => 16/673589
[patent_app_country] => US
[patent_app_date] => 2019-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 24079
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16673589
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/673589 | Coding method and apparatus, and device | Nov 3, 2019 | Issued |
Array
(
[id] => 15566497
[patent_doc_number] => 20200067660
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-27
[patent_title] => APPARATUS AND METHOD FOR AVOIDING DETERMINISTIC BLANKING OF SECURE TRAFFIC
[patent_app_type] => utility
[patent_app_number] => 16/667958
[patent_app_country] => US
[patent_app_date] => 2019-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4237
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667958
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/667958 | Apparatus and method for avoiding deterministic blanking of secure traffic | Oct 29, 2019 | Issued |
Array
(
[id] => 16638593
[patent_doc_number] => 10917115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-09
[patent_title] => Polar coding method and apparatus
[patent_app_type] => utility
[patent_app_number] => 16/664660
[patent_app_country] => US
[patent_app_date] => 2019-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 53931
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 3477
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664660
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/664660 | Polar coding method and apparatus | Oct 24, 2019 | Issued |
Array
(
[id] => 17892593
[patent_doc_number] => 11455564
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-27
[patent_title] => Qubit allocation for noisy intermediate-scale quantum computers
[patent_app_type] => utility
[patent_app_number] => 16/659406
[patent_app_country] => US
[patent_app_date] => 2019-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 12284
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16659406
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/659406 | Qubit allocation for noisy intermediate-scale quantum computers | Oct 20, 2019 | Issued |
Array
(
[id] => 18303680
[patent_doc_number] => 11625586
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-11
[patent_title] => Realization of neural networks with ternary inputs and ternary weights in NAND memory arrays
[patent_app_type] => utility
[patent_app_number] => 16/653365
[patent_app_country] => US
[patent_app_date] => 2019-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 45
[patent_no_of_words] => 18471
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16653365
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/653365 | Realization of neural networks with ternary inputs and ternary weights in NAND memory arrays | Oct 14, 2019 | Issued |
Array
(
[id] => 17003236
[patent_doc_number] => 11082067
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-08-03
[patent_title] => System and method for determining bit types for polar encoding and decoding
[patent_app_type] => utility
[patent_app_number] => 16/592381
[patent_app_country] => US
[patent_app_date] => 2019-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 19
[patent_no_of_words] => 15583
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592381
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/592381 | System and method for determining bit types for polar encoding and decoding | Oct 2, 2019 | Issued |
Array
(
[id] => 16653172
[patent_doc_number] => 10930363
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-02-23
[patent_title] => TSV auto repair scheme on stacked die
[patent_app_type] => utility
[patent_app_number] => 16/590789
[patent_app_country] => US
[patent_app_date] => 2019-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5237
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16590789
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/590789 | TSV auto repair scheme on stacked die | Oct 1, 2019 | Issued |
Array
(
[id] => 16803957
[patent_doc_number] => 10998919
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-04
[patent_title] => Coded stream processing
[patent_app_type] => utility
[patent_app_number] => 16/590461
[patent_app_country] => US
[patent_app_date] => 2019-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6225
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16590461
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/590461 | Coded stream processing | Oct 1, 2019 | Issued |
Array
(
[id] => 15416597
[patent_doc_number] => 20200028621
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-23
[patent_title] => APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN COMMUNICATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/588286
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5748
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588286
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/588286 | Apparatus and method for transmitting and receiving data in communication system | Sep 29, 2019 | Issued |
Array
(
[id] => 16378043
[patent_doc_number] => 20200326885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-15
[patent_title] => PROBABILISTICALLY SELECTING STORAGE UNITS BASED ON LATENCY OR THROUGHPUT IN A DISPERSED STORAGE NETWORK
[patent_app_type] => utility
[patent_app_number] => 16/571525
[patent_app_country] => US
[patent_app_date] => 2019-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16042
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571525
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/571525 | Probabilistically selecting storage units based on latency or throughput in a dispersed storage network | Sep 15, 2019 | Issued |
Array
(
[id] => 17846535
[patent_doc_number] => 11435905
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-09-06
[patent_title] => Accurate and efficient DNA-based storage of electronic data
[patent_app_type] => utility
[patent_app_number] => 16/571179
[patent_app_country] => US
[patent_app_date] => 2019-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 10587
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571179
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/571179 | Accurate and efficient DNA-based storage of electronic data | Sep 14, 2019 | Issued |
Array
(
[id] => 15333875
[patent_doc_number] => 20200007267
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-02
[patent_title] => Check Positions Within a Transport Block
[patent_app_type] => utility
[patent_app_number] => 16/569795
[patent_app_country] => US
[patent_app_date] => 2019-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7282
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569795
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/569795 | Check positions within a transport block | Sep 12, 2019 | Issued |
Array
(
[id] => 16417642
[patent_doc_number] => 10825542
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-11-03
[patent_title] => Method for efficiently checking storage units of flash memory of flash memory device and corresponding electronic device executing the method
[patent_app_type] => utility
[patent_app_number] => 16/568260
[patent_app_country] => US
[patent_app_date] => 2019-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5149
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568260
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/568260 | Method for efficiently checking storage units of flash memory of flash memory device and corresponding electronic device executing the method | Sep 11, 2019 | Issued |
Array
(
[id] => 16879894
[patent_doc_number] => 11030043
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-08
[patent_title] => Error correction circuit and memory system
[patent_app_type] => utility
[patent_app_number] => 16/569369
[patent_app_country] => US
[patent_app_date] => 2019-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5239
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569369
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/569369 | Error correction circuit and memory system | Sep 11, 2019 | Issued |
Array
(
[id] => 16637812
[patent_doc_number] => 10916326
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-02-09
[patent_title] => System and method for determining DIMM failures using on-DIMM voltage regulators
[patent_app_type] => utility
[patent_app_number] => 16/569543
[patent_app_country] => US
[patent_app_date] => 2019-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6497
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569543
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/569543 | System and method for determining DIMM failures using on-DIMM voltage regulators | Sep 11, 2019 | Issued |
Array
(
[id] => 16789878
[patent_doc_number] => 10992321
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-27
[patent_title] => Data processing device and data processing method
[patent_app_type] => utility
[patent_app_number] => 16/566144
[patent_app_country] => US
[patent_app_date] => 2019-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 220
[patent_figures_cnt] => 220
[patent_no_of_words] => 52984
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 559
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566144
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/566144 | Data processing device and data processing method | Sep 9, 2019 | Issued |
Array
(
[id] => 15533889
[patent_doc_number] => 20200059250
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-20
[patent_title] => DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 16/566195
[patent_app_country] => US
[patent_app_date] => 2019-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 53278
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 489
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566195
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/566195 | Data processing device and data processing method | Sep 9, 2019 | Issued |
Array
(
[id] => 15276087
[patent_doc_number] => 20190386778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => METHOD, APPARATUS, AND DEVICE FOR DETERMINING POLAR CODE ENCODING AND DECODING
[patent_app_type] => utility
[patent_app_number] => 16/558285
[patent_app_country] => US
[patent_app_date] => 2019-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10454
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558285
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/558285 | Method, apparatus, and device for determining polar code encoding and decoding | Sep 1, 2019 | Issued |