Search

John B Sotomayor

Examiner (ID: 832, Phone: (571)272-6978 , Office: P/3646 )

Most Active Art Unit
3662
Art Unit(s)
3662, 3642, 2202, 3646, 2201, 3641
Total Applications
2701
Issued Applications
2479
Pending Applications
70
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16247439 [patent_doc_number] => 10746790 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-18 [patent_title] => Constrained pseudorandom test pattern for in-system logic built-in self-test [patent_app_type] => utility [patent_app_number] => 16/363382 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363382 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363382
Constrained pseudorandom test pattern for in-system logic built-in self-test Mar 24, 2019 Issued
Array ( [id] => 14906187 [patent_doc_number] => 20190296859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => APPARATUS AND METHOD FOR DECODING USING CYCLIC REDUNDANCY CHECK IN WIRELESS COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 16/362412 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/362412
Apparatus and method for decoding using cyclic redundancy check in wireless communication system Mar 21, 2019 Issued
Array ( [id] => 16273153 [patent_doc_number] => 20200274641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => OPTIMIZING DELAY-SENSITIVE NETWORK-BASED COMMUNICATIONS WITH LATENCY GUIDANCE [patent_app_type] => utility [patent_app_number] => 16/284936 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16284936 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/284936
Optimizing delay-sensitive network-based communications with latency guidance Feb 24, 2019 Issued
Array ( [id] => 15719387 [patent_doc_number] => 20200106461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => BURST ERROR TOLERANT DECODER AND RELATED SYSTEMS, METHODS, AND DEVICES [patent_app_type] => utility [patent_app_number] => 16/283634 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283634 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283634
Burst error tolerant decoder and related systems, methods, and devices Feb 21, 2019 Issued
Array ( [id] => 16478217 [patent_doc_number] => 10853165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Fault resilient apparatus and method [patent_app_type] => utility [patent_app_number] => 16/281388 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10502 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281388 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281388
Fault resilient apparatus and method Feb 20, 2019 Issued
Array ( [id] => 14443665 [patent_doc_number] => 20190179706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => TECHNIQUES FOR OPTIMIZING METADATA RESILIENCY AND PERFORMANCE [patent_app_type] => utility [patent_app_number] => 16/277125 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277125
Techniques for optimizing metadata resiliency and performance Feb 14, 2019 Issued
Array ( [id] => 16002667 [patent_doc_number] => 20200177204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => APPARATUS AND METHOD FOR OFFSET OPTIMIZATION FOR LOW-DENSITY PARITY-CHECK (LDPC) CODE [patent_app_type] => utility [patent_app_number] => 16/269190 [patent_app_country] => US [patent_app_date] => 2019-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16269190 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/269190
Apparatus and method for offset optimization for low-density parity-check (LDPC) code Feb 5, 2019 Issued
Array ( [id] => 14872553 [patent_doc_number] => 20190286518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/268727 [patent_app_country] => US [patent_app_date] => 2019-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16268727 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/268727
Memory system Feb 5, 2019 Issued
Array ( [id] => 14444389 [patent_doc_number] => 20190180068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => ENHANCED MATRIX SYMBOL ERROR CORRECTION METHOD [patent_app_type] => utility [patent_app_number] => 16/268721 [patent_app_country] => US [patent_app_date] => 2019-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16268721 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/268721
Enhanced matrix symbol error correction method Feb 5, 2019 Issued
Array ( [id] => 16187674 [patent_doc_number] => 10721020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Parity frame [patent_app_type] => utility [patent_app_number] => 16/266626 [patent_app_country] => US [patent_app_date] => 2019-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3940 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266626 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/266626
Parity frame Feb 3, 2019 Issued
Array ( [id] => 15824595 [patent_doc_number] => 10637501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Forward error correction (FEC) emulator [patent_app_type] => utility [patent_app_number] => 16/262148 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262148
Forward error correction (FEC) emulator Jan 29, 2019 Issued
Array ( [id] => 14872699 [patent_doc_number] => 20190286591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/254436 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16254436 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/254436
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS Jan 21, 2019 Abandoned
Array ( [id] => 14286755 [patent_doc_number] => 20190140662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => POLAR CODING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 16/236002 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236002
Polar coding method and apparatus Dec 27, 2018 Issued
Array ( [id] => 18235214 [patent_doc_number] => 11599773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Neural networks and systems for decoding encoded data [patent_app_type] => utility [patent_app_number] => 16/233576 [patent_app_country] => US [patent_app_date] => 2018-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16233576 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/233576
Neural networks and systems for decoding encoded data Dec 26, 2018 Issued
Array ( [id] => 16219288 [patent_doc_number] => 10735116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Margin test methods and circuits [patent_app_type] => utility [patent_app_number] => 16/228470 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228470 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228470
Margin test methods and circuits Dec 19, 2018 Issued
Array ( [id] => 14411359 [patent_doc_number] => 20190171523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => ERASED MEMORY PAGE RECONSTRUCTION USING DISTRIBUTED CODING FOR MULTIPLE DIMENSIONAL PARITIES [patent_app_type] => utility [patent_app_number] => 16/228431 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228431
Erased memory page reconstruction using distributed coding for multiple dimensional parities Dec 19, 2018 Issued
Array ( [id] => 16410893 [patent_doc_number] => 10819466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Digital radio channel error detection [patent_app_type] => utility [patent_app_number] => 16/223718 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223718 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223718
Digital radio channel error detection Dec 17, 2018 Issued
Array ( [id] => 17026251 [patent_doc_number] => 20210250123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => USER STATION FOR A SERIAL COMMUNICATION NETWORK AND METHOD FOR CORRECTING INDIVIDUAL ERRORS IN A MESSAGE OF A SERIAL COMMUNICATION NETWORK [patent_app_type] => utility [patent_app_number] => 16/966730 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16966730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/966730
User station for a serial communication network and method for correcting individual errors in a message of a serial communication network Dec 17, 2018 Issued
Array ( [id] => 16294331 [patent_doc_number] => 10771189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Forward error correction mechanism for data transmission across multi-lane links [patent_app_type] => utility [patent_app_number] => 16/224583 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 16535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16224583 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/224583
Forward error correction mechanism for data transmission across multi-lane links Dec 17, 2018 Issued
Array ( [id] => 16077533 [patent_doc_number] => 20200192753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => SELF CORRECTING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/221635 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221635 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/221635
Self correcting memory device Dec 16, 2018 Issued
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