Search

John B Sotomayor

Examiner (ID: 832, Phone: (571)272-6978 , Office: P/3646 )

Most Active Art Unit
3662
Art Unit(s)
3662, 3642, 2202, 3646, 2201, 3641
Total Applications
2701
Issued Applications
2479
Pending Applications
70
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12598023 [patent_doc_number] => 20180091171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/627541 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627541
Memory controller, semiconductor memory system and operating method thereof Jun 19, 2017 Issued
Array ( [id] => 13631219 [patent_doc_number] => 20180367162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => CPU Error Remediation During Erasure Code Encoding [patent_app_type] => utility [patent_app_number] => 15/626043 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15626043 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/626043
CPU error remediation during erasure code encoding Jun 15, 2017 Issued
Array ( [id] => 13631389 [patent_doc_number] => 20180367248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => USING SLICE ROUTERS FOR IMPROVED STORAGE PLACEMENT DETERMINATION [patent_app_type] => utility [patent_app_number] => 15/624771 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/624771
Using slice routers for improved storage placement determination Jun 15, 2017 Issued
Array ( [id] => 15016899 [patent_doc_number] => 10454620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Facilitating notifications to indicate failed code block groups in 5G or other next generation networks [patent_app_type] => utility [patent_app_number] => 15/625751 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15307 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625751 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/625751
Facilitating notifications to indicate failed code block groups in 5G or other next generation networks Jun 15, 2017 Issued
Array ( [id] => 16171547 [patent_doc_number] => 10713117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Storage system and method for controlling storage system [patent_app_type] => utility [patent_app_number] => 16/327349 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 16777 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16327349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/327349
Storage system and method for controlling storage system Jun 14, 2017 Issued
Array ( [id] => 13710503 [patent_doc_number] => 20170366206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => SYSTEMS AND METHODS FOR RATE MATCHING WHEN USING GENERAL POLAR CODES [patent_app_type] => utility [patent_app_number] => 15/607584 [patent_app_country] => US [patent_app_date] => 2017-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607584 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/607584
Systems and methods for rate matching when using general polar codes May 28, 2017 Issued
Array ( [id] => 13696261 [patent_doc_number] => 20170359085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => CODING APPARATUS, TRANSPORT APPARATUS, AND CODING METHOD [patent_app_type] => utility [patent_app_number] => 15/606893 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606893 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/606893
CODING APPARATUS, TRANSPORT APPARATUS, AND CODING METHOD May 25, 2017 Abandoned
Array ( [id] => 15108383 [patent_doc_number] => 10475521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Semiconductor storage device and test method thereof using a common bit line [patent_app_type] => utility [patent_app_number] => 15/606637 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8128 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 770 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/606637
Semiconductor storage device and test method thereof using a common bit line May 25, 2017 Issued
Array ( [id] => 13582943 [patent_doc_number] => 20180343020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => GENERALIZED LOW-DENSITY PARITY-CHECK (GLDPC) CODE WITH VARIABLE LENGTH CONSTITUENTS [patent_app_type] => utility [patent_app_number] => 15/607234 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607234 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/607234
Generalized low-density parity-check (GLDPC) code with variable length constituents May 25, 2017 Issued
Array ( [id] => 14302241 [patent_doc_number] => 10291258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Error correcting code for correcting single symbol errors and detecting double bit errors [patent_app_type] => utility [patent_app_number] => 15/605310 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5885 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605310 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/605310
Error correcting code for correcting single symbol errors and detecting double bit errors May 24, 2017 Issued
Array ( [id] => 13185941 [patent_doc_number] => 10108490 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-23 [patent_title] => Decoding method, memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 15/604661 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 15003 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604661 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604661
Decoding method, memory storage device and memory control circuit unit May 24, 2017 Issued
Array ( [id] => 14916249 [patent_doc_number] => 10429441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Efficient test architecture for multi-die chips [patent_app_type] => utility [patent_app_number] => 15/603779 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13172 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603779 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603779
Efficient test architecture for multi-die chips May 23, 2017 Issued
Array ( [id] => 13895009 [patent_doc_number] => 10200063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Memory controller, semiconductor memory system and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/599576 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 11921 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599576 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599576
Memory controller, semiconductor memory system and operating method thereof May 18, 2017 Issued
Array ( [id] => 12718672 [patent_doc_number] => 20180131390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE PERFORMING RANDOMIZATION OPERATION [patent_app_type] => utility [patent_app_number] => 15/596803 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/596803
Semiconductor memory device performing randomization operation May 15, 2017 Issued
Array ( [id] => 14739925 [patent_doc_number] => 10389379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Error correcting code testing [patent_app_type] => utility [patent_app_number] => 15/594322 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7621 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594322 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/594322
Error correcting code testing May 11, 2017 Issued
Array ( [id] => 11946561 [patent_doc_number] => 20170250712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'QC-LDPC Coding Methods And Apparatus' [patent_app_type] => utility [patent_app_number] => 15/594239 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9658 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594239 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/594239
QC-LDPC coding methods and apparatus May 11, 2017 Issued
Array ( [id] => 13449049 [patent_doc_number] => 20180276067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => DATA PROTECTING METHOD AND MEMORY STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/591116 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591116 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/591116
Data protecting method and memory storage device May 9, 2017 Issued
Array ( [id] => 13978027 [patent_doc_number] => 10218387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => ECC memory controller supporting secure and non-secure regions [patent_app_type] => utility [patent_app_number] => 15/589199 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7483 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589199 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589199
ECC memory controller supporting secure and non-secure regions May 7, 2017 Issued
Array ( [id] => 14570927 [patent_doc_number] => 20190213070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => COMMUNICATION APPARATUS, COMMUNICATION METHOD, PROGRAM, AND COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 16/099296 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16099296 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/099296
Communication apparatus, communication method, program, and communication system May 1, 2017 Issued
Array ( [id] => 14766513 [patent_doc_number] => 10394653 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-27 [patent_title] => Computing in parallel processing environments [patent_app_type] => utility [patent_app_number] => 15/584299 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6428 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15584299 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/584299
Computing in parallel processing environments May 1, 2017 Issued
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