Search

John B Sotomayor

Examiner (ID: 832, Phone: (571)272-6978 , Office: P/3646 )

Most Active Art Unit
3662
Art Unit(s)
3662, 3642, 2202, 3646, 2201, 3641
Total Applications
2701
Issued Applications
2479
Pending Applications
70
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12206976 [patent_doc_number] => 20180052203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'METHOD FOR ENABLING CPU-JTAG DEBUGGER CONNECTION OR IMPROVING ITS PERFORMANCE FOR MULTI-CLOCK DESIGNS RUNNING ON FPGA OR EMULATION SYSTEMS' [patent_app_type] => utility [patent_app_number] => 15/414107 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2467 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414107 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414107
METHOD FOR ENABLING CPU-JTAG DEBUGGER CONNECTION OR IMPROVING ITS PERFORMANCE FOR MULTI-CLOCK DESIGNS RUNNING ON FPGA OR EMULATION SYSTEMS Jan 23, 2017 Abandoned
Array ( [id] => 15612347 [patent_doc_number] => 10587248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature [patent_app_type] => utility [patent_app_number] => 15/414600 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3211 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414600 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414600
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Jan 23, 2017 Issued
Array ( [id] => 14739927 [patent_doc_number] => 10389380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Efficient data path architecture for flash devices configured to perform multi-pass programming [patent_app_type] => utility [patent_app_number] => 15/412353 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15412353 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/412353
Efficient data path architecture for flash devices configured to perform multi-pass programming Jan 22, 2017 Issued
Array ( [id] => 12817606 [patent_doc_number] => 20180164374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => INTERFACE CHIP AND TEST METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 15/411063 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411063 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411063
Interface chip and test method therefor Jan 19, 2017 Issued
Array ( [id] => 13692011 [patent_doc_number] => 20170356960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => LOGIC ANALYZER, METHOD OF RETRIEVING DATA OF THE SAME, AND METHOD OF PERFORMANCE TESTING [patent_app_type] => utility [patent_app_number] => 15/411491 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411491 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411491
Logic analyzer for evaluating an electronic product, method of retrieving data of the same, and method of performance testing Jan 19, 2017 Issued
Array ( [id] => 15058981 [patent_doc_number] => 10459795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => RAID systems and methods for improved data recovery performance [patent_app_type] => utility [patent_app_number] => 15/410509 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7237 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410509 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/410509
RAID systems and methods for improved data recovery performance Jan 18, 2017 Issued
Array ( [id] => 14766503 [patent_doc_number] => 10394648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Method to deliver in-DRAM ECC information through DDR bus [patent_app_type] => utility [patent_app_number] => 15/410752 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14426 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410752 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/410752
Method to deliver in-DRAM ECC information through DDR bus Jan 18, 2017 Issued
Array ( [id] => 11761010 [patent_doc_number] => 20170207879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING PROGRAM, AND INFORMATION PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 15/408286 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3321 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408286
Information processing system, information processing program, and information processing method Jan 16, 2017 Issued
Array ( [id] => 13307911 [patent_doc_number] => 20180205492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => DIGITAL RADIO CHANNEL ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 15/408081 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408081 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408081
Digital radio channel error detection Jan 16, 2017 Issued
Array ( [id] => 16387374 [patent_doc_number] => 10812227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Method for transferring data via a disrupted radio channel and receiving unit and transmitting unit for use in the method [patent_app_type] => utility [patent_app_number] => 16/082369 [patent_app_country] => US [patent_app_date] => 2017-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5488 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16082369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/082369
Method for transferring data via a disrupted radio channel and receiving unit and transmitting unit for use in the method Jan 10, 2017 Issued
Array ( [id] => 11953317 [patent_doc_number] => 20170257468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'APPARATUS AND METHOD FOR TRANSMITTING MOVING PICTURE EXPERTS GROUP (MPEG)-2 TRANSPORT STREAM (TS) BROADCASTING DATA' [patent_app_type] => utility [patent_app_number] => 15/403616 [patent_app_country] => US [patent_app_date] => 2017-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6477 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403616 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/403616
APPARATUS AND METHOD FOR TRANSMITTING MOVING PICTURE EXPERTS GROUP (MPEG)-2 TRANSPORT STREAM (TS) BROADCASTING DATA Jan 10, 2017 Abandoned
Array ( [id] => 16567397 [patent_doc_number] => 10892778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Encoding method and device and decoding method and device for structured LDPC [patent_app_type] => utility [patent_app_number] => 16/301290 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 24377 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 465 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16301290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/301290
Encoding method and device and decoding method and device for structured LDPC Jan 5, 2017 Issued
Array ( [id] => 11591662 [patent_doc_number] => 20170116073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'DETECTING SINGLE EVENT UPSETS AND STUCK-AT FAULTS IN RAM-BASED DATA PATH CONTROLLERS' [patent_app_type] => utility [patent_app_number] => 15/399646 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399646 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399646
Detecting single event upsets and stuck-at faults in RAM-based data path controllers Jan 4, 2017 Issued
Array ( [id] => 13291611 [patent_doc_number] => 10156995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Semiconductor memory devices and methods of operating the same [patent_app_type] => utility [patent_app_number] => 15/398409 [patent_app_country] => US [patent_app_date] => 2017-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 11719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/398409
Semiconductor memory devices and methods of operating the same Jan 3, 2017 Issued
Array ( [id] => 11516170 [patent_doc_number] => 20170083244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'MITIGATING THE IMPACT OF A SINGLE POINT OF FAILURE IN AN OBJECT STORE' [patent_app_type] => utility [patent_app_number] => 15/370155 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370155 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/370155
MITIGATING THE IMPACT OF A SINGLE POINT OF FAILURE IN AN OBJECT STORE Dec 5, 2016 Abandoned
Array ( [id] => 11653608 [patent_doc_number] => 20170149513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'Margin Test Methods and Circuits' [patent_app_type] => utility [patent_app_number] => 15/368805 [patent_app_country] => US [patent_app_date] => 2016-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7670 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15368805 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/368805
Margin test methods and circuits Dec 4, 2016 Issued
Array ( [id] => 15952871 [patent_doc_number] => 10664343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Memory controller, non-volatile memory, and method of controlling memory controller [patent_app_type] => utility [patent_app_number] => 16/072831 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 45 [patent_no_of_words] => 17315 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16072831 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/072831
Memory controller, non-volatile memory, and method of controlling memory controller Nov 30, 2016 Issued
Array ( [id] => 13054951 [patent_doc_number] => 10048864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Dynamically configuring erasure code redundancy and distribution [patent_app_type] => utility [patent_app_number] => 15/365287 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6121 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365287 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365287
Dynamically configuring erasure code redundancy and distribution Nov 29, 2016 Issued
Array ( [id] => 11958186 [patent_doc_number] => 20170262338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'OPTICAL DISC APPARATUS AND OPTICAL DISC PROVIDED WITH QUALITY ESTIMETOR FOR GENERATING QUALITY VALUE OF RECORDING QUALITY OF OPTICAL DISC' [patent_app_type] => utility [patent_app_number] => 15/355735 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5652 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15355735 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/355735
Optical disc apparatus and optical disc in which user data is recorded in a first space in units of a first length and management information is recorded in a second space in units of a second length different from the first length Nov 17, 2016 Issued
Array ( [id] => 11965705 [patent_doc_number] => 20170269858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'METHOD AND SYSTEM FOR DATA PROTECTION IN NVMe INTERFACE' [patent_app_type] => utility [patent_app_number] => 15/346782 [patent_app_country] => US [patent_app_date] => 2016-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2926 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15346782 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/346782
METHOD AND SYSTEM FOR DATA PROTECTION IN NVMe INTERFACE Nov 8, 2016 Abandoned
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