Search

John B Sotomayor

Examiner (ID: 832, Phone: (571)272-6978 , Office: P/3646 )

Most Active Art Unit
3662
Art Unit(s)
3662, 3642, 2202, 3646, 2201, 3641
Total Applications
2701
Issued Applications
2479
Pending Applications
70
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12617256 [patent_doc_number] => 20180097582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => AN APPARATUS AND A METHOD FOR A REGENERATIVE NETWORK NODE BETWEEN A FIRST AND A SECOND LINK PORTION [patent_app_type] => utility [patent_app_number] => 15/564893 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15564893 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/564893
Apparatus and a method for a regenerative network node between a first and a second link portion Apr 21, 2016 Issued
Array ( [id] => 14302239 [patent_doc_number] => 10291257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Transmitter and method for generating additional parity thereof [patent_app_type] => utility [patent_app_number] => 15/130040 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 33042 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15130040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/130040
Transmitter and method for generating additional parity thereof Apr 14, 2016 Issued
Array ( [id] => 11051486 [patent_doc_number] => 20160248446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF' [patent_app_type] => utility [patent_app_number] => 15/099825 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 37774 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15099825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/099825
Transmitter and method for generating additional parity thereof Apr 14, 2016 Issued
Array ( [id] => 12480186 [patent_doc_number] => 09991993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Time offset validation of components with independent silicon clocks [patent_app_type] => utility [patent_app_number] => 15/088735 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 25663 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15088735 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/088735
Time offset validation of components with independent silicon clocks Mar 31, 2016 Issued
Array ( [id] => 13156315 [patent_doc_number] => 10094875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-09 [patent_title] => Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design [patent_app_type] => utility [patent_app_number] => 15/087871 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 14474 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087871 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/087871
Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design Mar 30, 2016 Issued
Array ( [id] => 13067719 [patent_doc_number] => 10054636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Device, system and method to support communication of test, debug or trace information with an external input/output interface [patent_app_type] => utility [patent_app_number] => 15/085945 [patent_app_country] => US [patent_app_date] => 2016-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11603 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15085945 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/085945
Device, system and method to support communication of test, debug or trace information with an external input/output interface Mar 29, 2016 Issued
Array ( [id] => 11984543 [patent_doc_number] => 20170288698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'POWER SAVING FOR BIT FLIPPING DECODING ALGORITHM IN LDPC DECODER' [patent_app_type] => utility [patent_app_number] => 15/083310 [patent_app_country] => US [patent_app_date] => 2016-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1558 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083310 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/083310
POWER SAVING FOR BIT FLIPPING DECODING ALGORITHM IN LDPC DECODER Mar 28, 2016 Abandoned
Array ( [id] => 11974429 [patent_doc_number] => 20170278583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'FUSEBOX-BASED MEMORY REPAIR' [patent_app_type] => utility [patent_app_number] => 15/081640 [patent_app_country] => US [patent_app_date] => 2016-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6231 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15081640 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/081640
Fusebox-based memory repair using redundant memories Mar 24, 2016 Issued
Array ( [id] => 11057940 [patent_doc_number] => 20160254903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'CIRCUIT FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY INCREMENTAL SAMPLING, JITTER DETECTION, AND EXCEPTION HANDLING' [patent_app_type] => utility [patent_app_number] => 15/078939 [patent_app_country] => US [patent_app_date] => 2016-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6796 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15078939 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/078939
Circuit for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handling Mar 22, 2016 Issued
Array ( [id] => 16921547 [patent_doc_number] => 20210194639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => FLEXIBLY DETERMINING A REORDERING VALUE FOR RADIO LINK CONTROL PROTOCOL DATA UNIT RETRANSMISSIONS [patent_app_type] => utility [patent_app_number] => 16/077715 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16077715 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/077715
FLEXIBLY DETERMINING A REORDERING VALUE FOR RADIO LINK CONTROL PROTOCOL DATA UNIT RETRANSMISSIONS Mar 17, 2016 Abandoned
Array ( [id] => 11951365 [patent_doc_number] => 20170255516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'Field-Repair System and Method of Mask-Programmed Read-Only Memory' [patent_app_type] => utility [patent_app_number] => 15/062120 [patent_app_country] => US [patent_app_date] => 2016-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062120 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/062120
Field-Repair System and Method of Mask-Programmed Read-Only Memory Mar 5, 2016 Abandoned
Array ( [id] => 14302237 [patent_doc_number] => 10291256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Transmitter and method for generating additional parity thereof [patent_app_type] => utility [patent_app_number] => 15/058415 [patent_app_country] => US [patent_app_date] => 2016-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 32776 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058415 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/058415
Transmitter and method for generating additional parity thereof Mar 1, 2016 Issued
Array ( [id] => 11048906 [patent_doc_number] => 20160245864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'Automatic test apparatus for functional digital testing of multiple semiconductor integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 15/046283 [patent_app_country] => US [patent_app_date] => 2016-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5324 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/046283
Automatic test apparatus for functional digital testing of multiple semiconductor integrated circuit devices Feb 16, 2016 Abandoned
Array ( [id] => 14152889 [patent_doc_number] => 10256838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Decoding apparatus, decoding method, and computer program product [patent_app_type] => utility [patent_app_number] => 15/044569 [patent_app_country] => US [patent_app_date] => 2016-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 10859 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15044569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/044569
Decoding apparatus, decoding method, and computer program product Feb 15, 2016 Issued
Array ( [id] => 11869249 [patent_doc_number] => 20170236534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'Write Current Switching in a Data Storage Device' [patent_app_type] => utility [patent_app_number] => 15/043801 [patent_app_country] => US [patent_app_date] => 2016-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15043801 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/043801
Write current switching in a data storage device Feb 14, 2016 Issued
Array ( [id] => 13110169 [patent_doc_number] => 10073738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => XF erasure code for distributed storage systems [patent_app_type] => utility [patent_app_number] => 15/017389 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 11013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15017389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/017389
XF erasure code for distributed storage systems Feb 4, 2016 Issued
Array ( [id] => 13284383 [patent_doc_number] => 10153786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-11 [patent_title] => Iterative decoder with dynamically-variable performance [patent_app_type] => utility [patent_app_number] => 15/012066 [patent_app_country] => US [patent_app_date] => 2016-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3820 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15012066 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/012066
Iterative decoder with dynamically-variable performance Jan 31, 2016 Issued
Array ( [id] => 11824127 [patent_doc_number] => 20170213064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'ENHANCED MATRIX SYMBOL ERROR CORRECTION METHOD' [patent_app_type] => utility [patent_app_number] => 15/006561 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006561 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006561
Enhanced matrix symbol error correction method Jan 25, 2016 Issued
Array ( [id] => 11496055 [patent_doc_number] => 20170070240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'MEMORY SYSTEM INCLUDING ERROR CORRECTOR AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/005237 [patent_app_country] => US [patent_app_date] => 2016-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15005237 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/005237
MEMORY SYSTEM INCLUDING ERROR CORRECTOR AND OPERATING METHOD THEREOF Jan 24, 2016 Abandoned
Array ( [id] => 14559945 [patent_doc_number] => 10348448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Transmitter and repetition method thereof [patent_app_type] => utility [patent_app_number] => 15/003969 [patent_app_country] => US [patent_app_date] => 2016-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 68348 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15003969 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/003969
Transmitter and repetition method thereof Jan 21, 2016 Issued
Menu