Search

John B Sotomayor

Examiner (ID: 832, Phone: (571)272-6978 , Office: P/3646 )

Most Active Art Unit
3662
Art Unit(s)
3662, 3642, 2202, 3646, 2201, 3641
Total Applications
2701
Issued Applications
2479
Pending Applications
70
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9926369 [patent_doc_number] => 08984355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Efficiency of compression of data pages' [patent_app_type] => utility [patent_app_number] => 13/707555 [patent_app_country] => US [patent_app_date] => 2012-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4719 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13707555 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/707555
Efficiency of compression of data pages Dec 5, 2012 Issued
Array ( [id] => 9520561 [patent_doc_number] => 20140157054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'MEMORY ERROR IDENTIFICATION BASED ON CORRUPTED SYMBOL PATTERNS' [patent_app_type] => utility [patent_app_number] => 13/689814 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5631 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13689814 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/689814
Memory error identification based on corrupted symbol patterns Nov 29, 2012 Issued
Array ( [id] => 10003120 [patent_doc_number] => 09047215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-02 [patent_title] => 'Method and system for reducing the effect of component recovery' [patent_app_type] => utility [patent_app_number] => 13/682727 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12511 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13682727 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/682727
Method and system for reducing the effect of component recovery Nov 19, 2012 Issued
Array ( [id] => 10591262 [patent_doc_number] => 09312885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Nonvolatile semiconductor memory system error correction capability of which is improved' [patent_app_type] => utility [patent_app_number] => 13/671936 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6019 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671936 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671936
Nonvolatile semiconductor memory system error correction capability of which is improved Nov 7, 2012 Issued
Array ( [id] => 9826090 [patent_doc_number] => 08935586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Staggered start of BIST controllers and BIST engines' [patent_app_type] => utility [patent_app_number] => 13/671605 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9058 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671605 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671605
Staggered start of BIST controllers and BIST engines Nov 7, 2012 Issued
Array ( [id] => 9465463 [patent_doc_number] => 20140129890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'Test Pattern Optimization for LDPC Based Flawscan' [patent_app_type] => utility [patent_app_number] => 13/672218 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672218 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672218
Test pattern optimization for LDPC based flawscan Nov 7, 2012 Issued
Array ( [id] => 9992723 [patent_doc_number] => 09037944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Method for selecting a LDPC candidate code' [patent_app_type] => utility [patent_app_number] => 13/671640 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671640 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671640
Method for selecting a LDPC candidate code Nov 7, 2012 Issued
Array ( [id] => 8816591 [patent_doc_number] => 20130117636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS' [patent_app_type] => utility [patent_app_number] => 13/670822 [patent_app_country] => US [patent_app_date] => 2012-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 24233 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670822 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/670822
SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS Nov 6, 2012 Abandoned
Array ( [id] => 10563323 [patent_doc_number] => 09287004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Semiconductor memory device and system having redundancy cells' [patent_app_type] => utility [patent_app_number] => 13/670792 [patent_app_country] => US [patent_app_date] => 2012-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 51 [patent_no_of_words] => 25412 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670792 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/670792
Semiconductor memory device and system having redundancy cells Nov 6, 2012 Issued
Array ( [id] => 9465478 [patent_doc_number] => 20140129905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'Flexible Low Density Parity Check Code Seed' [patent_app_type] => utility [patent_app_number] => 13/670393 [patent_app_country] => US [patent_app_date] => 2012-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670393 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/670393
Flexible Low Density Parity Check Code Seed Nov 5, 2012 Abandoned
Array ( [id] => 9800850 [patent_doc_number] => 20150012793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'METHOD FOR TRANSMITTING AND RECEIVING DATA IN WIRELESS ACCESS SYSTEM AND APPARATUS FOR SAME' [patent_app_type] => utility [patent_app_number] => 14/379697 [patent_app_country] => US [patent_app_date] => 2012-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11233 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14379697 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/379697
Method for transmitting and receiving data in wireless access system and apparatus for same Nov 5, 2012 Issued
Array ( [id] => 8929849 [patent_doc_number] => 20130185609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'NONVOLATILE MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/668607 [patent_app_country] => US [patent_app_date] => 2012-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9038 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13668607 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/668607
NONVOLATILE MEMORY SYSTEM Nov 4, 2012 Abandoned
Array ( [id] => 9451777 [patent_doc_number] => 20140122947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'Sequential Circuit with Error Detection' [patent_app_type] => utility [patent_app_number] => 13/664153 [patent_app_country] => US [patent_app_date] => 2012-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2685 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13664153 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/664153
Sequential circuit with error detection Oct 29, 2012 Issued
Array ( [id] => 10885625 [patent_doc_number] => 08910028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-09 [patent_title] => 'Implementation of LLR biasing method in non-binary iterative decoding' [patent_app_type] => utility [patent_app_number] => 13/660659 [patent_app_country] => US [patent_app_date] => 2012-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13660659 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/660659
Implementation of LLR biasing method in non-binary iterative decoding Oct 24, 2012 Issued
Array ( [id] => 9386267 [patent_doc_number] => 20140089750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'TEST COVERAGE OF INTEGRATED CIRCUITS WITH TEST VECTOR INPUT SPREADING' [patent_app_type] => utility [patent_app_number] => 13/628231 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5084 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628231 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628231
Test coverage of integrated circuits with test vector input spreading Sep 26, 2012 Issued
Array ( [id] => 9891652 [patent_doc_number] => 08977928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Apparatus and method for receiving a secure telegram' [patent_app_type] => utility [patent_app_number] => 13/627110 [patent_app_country] => US [patent_app_date] => 2012-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 7504 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13627110 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/627110
Apparatus and method for receiving a secure telegram Sep 25, 2012 Issued
Array ( [id] => 9071196 [patent_doc_number] => 20130262952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'MEMORY ARCHITECTURE FOR TURBO DECODER' [patent_app_type] => utility [patent_app_number] => 13/626317 [patent_app_country] => US [patent_app_date] => 2012-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13626317 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/626317
MEMORY ARCHITECTURE FOR TURBO DECODER Sep 24, 2012 Abandoned
Array ( [id] => 9386274 [patent_doc_number] => 20140089757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'LDPC Decoder With Fractional Local Iterations' [patent_app_type] => utility [patent_app_number] => 13/624927 [patent_app_country] => US [patent_app_date] => 2012-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13624927 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/624927
LDPC Decoder With Fractional Local Iterations Sep 21, 2012 Abandoned
Array ( [id] => 10139176 [patent_doc_number] => 09172505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-27 [patent_title] => 'Methods and apparatus for frame detection' [patent_app_type] => utility [patent_app_number] => 13/624095 [patent_app_country] => US [patent_app_date] => 2012-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5331 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13624095 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/624095
Methods and apparatus for frame detection Sep 20, 2012 Issued
Array ( [id] => 10503331 [patent_doc_number] => 09231734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Apparatus and method for transmitting and receiving data in communication/broadcasting system' [patent_app_type] => utility [patent_app_number] => 14/351066 [patent_app_country] => US [patent_app_date] => 2012-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 36882 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14351066 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/351066
Apparatus and method for transmitting and receiving data in communication/broadcasting system Sep 19, 2012 Issued
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