Search

John B Sotomayor

Examiner (ID: 832, Phone: (571)272-6978 , Office: P/3646 )

Most Active Art Unit
3662
Art Unit(s)
3662, 3642, 2202, 3646, 2201, 3641
Total Applications
2701
Issued Applications
2479
Pending Applications
70
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16561192 [patent_doc_number] => 20210006341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => Margin Test Methods and Circuits [patent_app_type] => utility [patent_app_number] => 16/930526 [patent_app_country] => US [patent_app_date] => 2020-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/930526
Margin test methods and circuits Jul 15, 2020 Issued
Array ( [id] => 17076813 [patent_doc_number] => 11113213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Determining write commands for deletion in a host interface [patent_app_type] => utility [patent_app_number] => 16/929416 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929416
Determining write commands for deletion in a host interface Jul 14, 2020 Issued
Array ( [id] => 16403139 [patent_doc_number] => 20200343997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => BANDWIDTH CONSTRAINED COMMUNICATION SYSTEMS WITH OPTIMIZED LOW-DENSITY PARITY-CHECK CODES [patent_app_type] => utility [patent_app_number] => 16/927615 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927615 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927615
Bandwidth constrained communication systems with optimized low-density parity-check codes Jul 12, 2020 Issued
Array ( [id] => 16979919 [patent_doc_number] => 20210224156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => ERROR CORRECTION CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/926000 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926000 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926000
Error correction circuit of semiconductor memory device and semiconductor memory device Jul 9, 2020 Issued
Array ( [id] => 17803898 [patent_doc_number] => 11418215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Electronic device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/923748 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 12141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923748 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/923748
Electronic device and method of operating the same Jul 7, 2020 Issued
Array ( [id] => 16957907 [patent_doc_number] => 11061770 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-13 [patent_title] => Reconstruction of logical pages in a storage system [patent_app_type] => utility [patent_app_number] => 16/916621 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 12776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916621
Reconstruction of logical pages in a storage system Jun 29, 2020 Issued
Array ( [id] => 17824337 [patent_doc_number] => 11429285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Content-based data storage [patent_app_type] => utility [patent_app_number] => 16/915856 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 9235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915856 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915856
Content-based data storage Jun 28, 2020 Issued
Array ( [id] => 17318561 [patent_doc_number] => 20210407611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => ERROR CORRECTION CODE CIRCUITS HAVING ONE-TO-ONE RELATIONSHIPS WITH INPUT/OUTPUT PADS AND RELATED APPARATUSES AND METHODS [patent_app_type] => utility [patent_app_number] => 16/912214 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/912214
Error correction code circuits having one-to-one relationships with input/output pads and related apparatuses and methods Jun 24, 2020 Issued
Array ( [id] => 17317074 [patent_doc_number] => 20210406123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 16/911197 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911197 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/911197
Apparatuses, systems, and methods for error correction Jun 23, 2020 Issued
Array ( [id] => 16918717 [patent_doc_number] => 20210191809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/909730 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/909730
Semiconductor memory devices and methods of operating semiconductor memory devices Jun 22, 2020 Issued
Array ( [id] => 17528656 [patent_doc_number] => 11301344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates [patent_app_type] => utility [patent_app_number] => 16/902755 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 20865 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902755 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902755
Aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates Jun 15, 2020 Issued
Array ( [id] => 17892403 [patent_doc_number] => 11455374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => System and method for combining differentiable partial differential equation solvers and graph neural networks for fluid flow prediction [patent_app_type] => utility [patent_app_number] => 16/895766 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895766
System and method for combining differentiable partial differential equation solvers and graph neural networks for fluid flow prediction Jun 7, 2020 Issued
Array ( [id] => 18155270 [patent_doc_number] => 11568251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Dynamic quantization for models run on edge devices [patent_app_type] => utility [patent_app_number] => 16/893831 [patent_app_country] => US [patent_app_date] => 2020-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9838 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893831 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/893831
Dynamic quantization for models run on edge devices Jun 4, 2020 Issued
Array ( [id] => 17277689 [patent_doc_number] => 20210383887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => POLAR NEURAL NETWORK DECODER FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/891565 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891565
Polar neural network decoder for memory devices Jun 2, 2020 Issued
Array ( [id] => 17048625 [patent_doc_number] => 11101820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-24 [patent_title] => Memory control method, memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 16/889808 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 11297 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/889808
Memory control method, memory storage device and memory control circuit unit Jun 1, 2020 Issued
Array ( [id] => 16765298 [patent_doc_number] => 20210110880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => STACKED MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/889378 [patent_app_country] => US [patent_app_date] => 2020-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/889378
Stacked memory device and memory system including the same May 31, 2020 Issued
Array ( [id] => 17528637 [patent_doc_number] => 11301325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Memory in integrity performance enhancement systems and methods [patent_app_type] => utility [patent_app_number] => 16/888449 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 11448 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/888449
Memory in integrity performance enhancement systems and methods May 28, 2020 Issued
Array ( [id] => 17501409 [patent_doc_number] => 11290127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Apparatus and method for offset optimization for low-density parity-check (LDPC) code [patent_app_type] => utility [patent_app_number] => 16/885566 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 10882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885566
Apparatus and method for offset optimization for low-density parity-check (LDPC) code May 27, 2020 Issued
Array ( [id] => 16470338 [patent_doc_number] => 20200371875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => HANDLING NON-CORRECTABLE ERRORS [patent_app_type] => utility [patent_app_number] => 16/882382 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882382 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882382
Handling non-correctable errors May 21, 2020 Issued
Array ( [id] => 17379889 [patent_doc_number] => 11237905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Pipelined read-modify-write operations in cache memory [patent_app_type] => utility [patent_app_number] => 16/874435 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7590 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874435 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874435
Pipelined read-modify-write operations in cache memory May 13, 2020 Issued
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