Search

John B Sotomayor

Examiner (ID: 832, Phone: (571)272-6978 , Office: P/3646 )

Most Active Art Unit
3662
Art Unit(s)
3662, 3642, 2202, 3646, 2201, 3641
Total Applications
2701
Issued Applications
2479
Pending Applications
70
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16270875 [patent_doc_number] => 20200272362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/871775 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871775 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/871775
Memory system and operating method thereof May 10, 2020 Issued
Array ( [id] => 17001327 [patent_doc_number] => 11080137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Error coalescing [patent_app_type] => utility [patent_app_number] => 16/870587 [patent_app_country] => US [patent_app_date] => 2020-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16870587 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/870587
Error coalescing May 7, 2020 Issued
Array ( [id] => 17652477 [patent_doc_number] => 11355213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Apparatus and method for verifying reliability of data read from memory device through clock modulation, and memory system including the same [patent_app_type] => utility [patent_app_number] => 16/868116 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15775 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868116
Apparatus and method for verifying reliability of data read from memory device through clock modulation, and memory system including the same May 5, 2020 Issued
Array ( [id] => 17516670 [patent_doc_number] => 11295830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Memory system and operating method of the memory system [patent_app_type] => utility [patent_app_number] => 16/865039 [patent_app_country] => US [patent_app_date] => 2020-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8404 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16865039 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/865039
Memory system and operating method of the memory system Apr 30, 2020 Issued
Array ( [id] => 17287841 [patent_doc_number] => 11204385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Transition fault test (TFT) clock receiver system [patent_app_type] => utility [patent_app_number] => 16/863906 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863906 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/863906
Transition fault test (TFT) clock receiver system Apr 29, 2020 Issued
Array ( [id] => 17717353 [patent_doc_number] => 11381357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Methods, systems and apparatus for scheduling of subframes and hybrid automatic repeat request (HARQ) feedback [patent_app_type] => utility [patent_app_number] => 16/863495 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 26113 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863495 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/863495
Methods, systems and apparatus for scheduling of subframes and hybrid automatic repeat request (HARQ) feedback Apr 29, 2020 Issued
Array ( [id] => 17180115 [patent_doc_number] => 11157358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Memory module, error correction method of memory controller controlling the same, and computing system including the same [patent_app_type] => utility [patent_app_number] => 16/861312 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 7786 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861312 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861312
Memory module, error correction method of memory controller controlling the same, and computing system including the same Apr 28, 2020 Issued
Array ( [id] => 17187275 [patent_doc_number] => 20210334160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => POOLING BLOCKS FOR ERASURE CODING WRITE GROUPS [patent_app_type] => utility [patent_app_number] => 16/858376 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16858376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/858376
Pooling blocks for erasure coding write groups Apr 23, 2020 Issued
Array ( [id] => 17572904 [patent_doc_number] => 11321173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Managing storage of multiple plane parity data in a memory sub-system [patent_app_type] => utility [patent_app_number] => 16/854429 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854429 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854429
Managing storage of multiple plane parity data in a memory sub-system Apr 20, 2020 Issued
Array ( [id] => 17164746 [patent_doc_number] => 11150842 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-19 [patent_title] => Dynamic memory controller and method for use therewith [patent_app_type] => utility [patent_app_number] => 16/853233 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853233 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/853233
Dynamic memory controller and method for use therewith Apr 19, 2020 Issued
Array ( [id] => 16192896 [patent_doc_number] => 20200233745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 16/841688 [patent_app_country] => US [patent_app_date] => 2020-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16841688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/841688
Flash memory apparatus and storage management method for flash memory Apr 6, 2020 Issued
Array ( [id] => 16400985 [patent_doc_number] => 20200341843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => MEMORY CONTROLLER, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/840581 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/840581
Memory controller, memory system including the same, and method of operating the memory controller Apr 5, 2020 Issued
Array ( [id] => 16193254 [patent_doc_number] => 20200234103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => NEURAL NETWORKS AND SYSTEMS FOR DECODING ENCODED DATA [patent_app_type] => utility [patent_app_number] => 16/839447 [patent_app_country] => US [patent_app_date] => 2020-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16839447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/839447
Neural networks and systems for decoding encoded data Apr 2, 2020 Issued
Array ( [id] => 16192909 [patent_doc_number] => 20200233758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => Integrated Circuit Chip with Cores Asymmetrically Oriented With Respect To Each Other [patent_app_type] => utility [patent_app_number] => 16/838176 [patent_app_country] => US [patent_app_date] => 2020-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16838176 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/838176
Integrated circuit chip with cores asymmetrically oriented with respect to each other Apr 1, 2020 Issued
Array ( [id] => 17941491 [patent_doc_number] => 11475950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Stressing algorithm for solving cell-to-cell variations in phase change memory [patent_app_type] => utility [patent_app_number] => 16/837770 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837770 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/837770
Stressing algorithm for solving cell-to-cell variations in phase change memory Mar 31, 2020 Issued
Array ( [id] => 16192970 [patent_doc_number] => 20200233819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => MEMORY RANK DESIGN FOR A MEMORY CHANNEL THAT IS OPTIMIZED FOR GRAPH APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/833322 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833322
Memory rank design for a memory channel that is optimized for graph applications Mar 26, 2020 Issued
Array ( [id] => 16684939 [patent_doc_number] => 10944435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-09 [patent_title] => Tearing save encoding [patent_app_type] => utility [patent_app_number] => 16/832325 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832325 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/832325
Tearing save encoding Mar 26, 2020 Issued
Array ( [id] => 17493242 [patent_doc_number] => 11282552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Memory buffer with data scrambling and error correction [patent_app_type] => utility [patent_app_number] => 16/831121 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 27 [patent_no_of_words] => 7185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831121 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831121
Memory buffer with data scrambling and error correction Mar 25, 2020 Issued
Array ( [id] => 17180120 [patent_doc_number] => 11157363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Distributed raid storage-device-assisted data rebuild system [patent_app_type] => utility [patent_app_number] => 16/829124 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12824 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829124 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/829124
Distributed raid storage-device-assisted data rebuild system Mar 24, 2020 Issued
Array ( [id] => 16181275 [patent_doc_number] => 20200228244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => METHOD AND DEVICE FOR RETRANSMISSION [patent_app_type] => utility [patent_app_number] => 16/828004 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828004 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828004
Method and device for retransmission Mar 23, 2020 Issued
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