Search

John B Sotomayor

Examiner (ID: 832, Phone: (571)272-6978 , Office: P/3646 )

Most Active Art Unit
3662
Art Unit(s)
3662, 3642, 2202, 3646, 2201, 3641
Total Applications
2701
Issued Applications
2479
Pending Applications
70
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16910393 [patent_doc_number] => 11042433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Data interpretation with modulation error ratio analysis [patent_app_type] => utility [patent_app_number] => 16/784075 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784075 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784075
Data interpretation with modulation error ratio analysis Feb 5, 2020 Issued
Array ( [id] => 17238367 [patent_doc_number] => 11182247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Encoding and storage node repairing method for minimum storage regenerating codes for distributed storage systems [patent_app_type] => utility [patent_app_number] => 16/776070 [patent_app_country] => US [patent_app_date] => 2020-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11650 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776070 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/776070
Encoding and storage node repairing method for minimum storage regenerating codes for distributed storage systems Jan 28, 2020 Issued
Array ( [id] => 17364974 [patent_doc_number] => 11231995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Providing data of a memory system based on an adjustable error rate [patent_app_type] => utility [patent_app_number] => 16/746786 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7784 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746786
Providing data of a memory system based on an adjustable error rate Jan 16, 2020 Issued
Array ( [id] => 16988527 [patent_doc_number] => 11075716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Repetition scheme for flexible bandwidth utilization [patent_app_type] => utility [patent_app_number] => 16/742620 [patent_app_country] => US [patent_app_date] => 2020-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7510 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16742620 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/742620
Repetition scheme for flexible bandwidth utilization Jan 13, 2020 Issued
Array ( [id] => 17817274 [patent_doc_number] => 11422886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Die level data redundancy in solid state storage devices [patent_app_type] => utility [patent_app_number] => 16/738098 [patent_app_country] => US [patent_app_date] => 2020-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8375 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738098 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/738098
Die level data redundancy in solid state storage devices Jan 8, 2020 Issued
Array ( [id] => 17001326 [patent_doc_number] => 11080136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Dropped write error detection [patent_app_type] => utility [patent_app_number] => 16/734449 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6859 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734449
Dropped write error detection Jan 5, 2020 Issued
Array ( [id] => 17423115 [patent_doc_number] => 11256569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Error correcting bits [patent_app_type] => utility [patent_app_number] => 16/732465 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8237 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732465 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732465
Error correcting bits Jan 1, 2020 Issued
Array ( [id] => 17180110 [patent_doc_number] => 11157353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Detecting single event upsets and stuck-at faults in RAM-based data path controllers [patent_app_type] => utility [patent_app_number] => 16/732596 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8004 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732596 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732596
Detecting single event upsets and stuck-at faults in RAM-based data path controllers Jan 1, 2020 Issued
Array ( [id] => 16684933 [patent_doc_number] => 10944429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-09 [patent_title] => Data accessing method using data protection with aid of parity check matrix having partial sequential information, and associated apparatus [patent_app_type] => utility [patent_app_number] => 16/732354 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732354 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732354
Data accessing method using data protection with aid of parity check matrix having partial sequential information, and associated apparatus Jan 1, 2020 Issued
Array ( [id] => 17001320 [patent_doc_number] => 11080130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/731807 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11171 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731807 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/731807
Semiconductor devices Dec 30, 2019 Issued
Array ( [id] => 17222843 [patent_doc_number] => 11175338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => System and method for compacting test data in many-core processors [patent_app_type] => utility [patent_app_number] => 16/732150 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7281 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732150 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732150
System and method for compacting test data in many-core processors Dec 30, 2019 Issued
Array ( [id] => 16577268 [patent_doc_number] => 20210011669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => CONTROLLER, MEMORY SYSTEM, AND OPERATING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 16/725770 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16725770 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/725770
Controller, memory system, and operating methods thereof Dec 22, 2019 Issued
Array ( [id] => 17802136 [patent_doc_number] => 11416437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities [patent_app_type] => utility [patent_app_number] => 16/720976 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4497 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720976
Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities Dec 18, 2019 Issued
Array ( [id] => 15809013 [patent_doc_number] => 20200127649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => DIGITAL LOGIC CIRCUIT FOR DETERRING RACE VIOLATIONS AT AN ARRAY TEST CONTROL BOUNDARY USING AN INVERTED ARRAY CLOCK SIGNAL FEATURE [patent_app_type] => utility [patent_app_number] => 16/721129 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721129 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721129
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Dec 18, 2019 Issued
Array ( [id] => 15809089 [patent_doc_number] => 20200127687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => DECODING OPTIMIZATION FOR CHANNEL MISMATCH [patent_app_type] => utility [patent_app_number] => 16/719408 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719408 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719408
Decoding optimization for channel mismatch Dec 17, 2019 Issued
Array ( [id] => 17269221 [patent_doc_number] => 11194646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Regression-based calibration and scanning of data units [patent_app_type] => utility [patent_app_number] => 16/702399 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7965 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702399 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702399
Regression-based calibration and scanning of data units Dec 2, 2019 Issued
Array ( [id] => 17002379 [patent_doc_number] => 11081201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Parallel test device [patent_app_type] => utility [patent_app_number] => 16/695203 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2116 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695203 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695203
Parallel test device Nov 25, 2019 Issued
Array ( [id] => 16788043 [patent_doc_number] => 10990476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Memory controller and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/696860 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 14368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696860 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696860
Memory controller and method of operating the same Nov 25, 2019 Issued
Array ( [id] => 16439104 [patent_doc_number] => 20200356430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/694472 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694472 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694472
Memory controller and method of operating the same Nov 24, 2019 Issued
Array ( [id] => 16403050 [patent_doc_number] => 20200343908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => APPARATUS AND METHOD FOR OPTIMIZING PHYSICAL LAYER PARAMETER [patent_app_type] => utility [patent_app_number] => 16/688546 [patent_app_country] => US [patent_app_date] => 2019-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16688546 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/688546
Apparatus and method for optimizing physical layer parameter Nov 18, 2019 Issued
Menu