Search

John B. Vigushin

Examiner (ID: 6446)

Most Active Art Unit
2841
Art Unit(s)
2827, 2103, 2835, 2841, 3662
Total Applications
656
Issued Applications
594
Pending Applications
37
Abandoned Applications
25

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12615831 [patent_doc_number] => 20180097107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => GATE CUT ON A VERTICAL FIELD EFFECT TRANSISTOR WITH A DEFINED-WIDTH INORGANIC MASK [patent_app_type] => utility [patent_app_number] => 15/814258 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814258 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814258
Gate cut on a vertical field effect transistor with a defined-width inorganic mask Nov 14, 2017 Issued
Array ( [id] => 16280329 [patent_doc_number] => 10763371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Thin-film transistor, method of manufacturing the same, and display device [patent_app_type] => utility [patent_app_number] => 15/813735 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 74 [patent_no_of_words] => 15477 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813735 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813735
Thin-film transistor, method of manufacturing the same, and display device Nov 14, 2017 Issued
Array ( [id] => 14525849 [patent_doc_number] => 10340195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Method to co-integrate SiGe and Si channels for finFET devices [patent_app_type] => utility [patent_app_number] => 15/813071 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813071 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813071
Method to co-integrate SiGe and Si channels for finFET devices Nov 13, 2017 Issued
Array ( [id] => 15316019 [patent_doc_number] => 10522727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Light emitting apparatus and method for producing the same [patent_app_type] => utility [patent_app_number] => 15/811622 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 18506 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811622 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811622
Light emitting apparatus and method for producing the same Nov 12, 2017 Issued
Array ( [id] => 12220984 [patent_doc_number] => 20180059344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SURFACE LIGHT EMITTING SEMICONDUCTOR LASER ELEMENT' [patent_app_type] => utility [patent_app_number] => 15/803382 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8306 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15803382 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/803382
Surface light emitting semiconductor laser element Nov 2, 2017 Issued
Array ( [id] => 12208635 [patent_doc_number] => 20180053861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'SEMICONDUCTOR OPTICAL PACKAGE AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/802271 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3316 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802271
Semiconductor optical package and method Nov 1, 2017 Issued
Array ( [id] => 12162591 [patent_doc_number] => 20180033857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'FINFETs WITH HIGH QUALITY SOURCE/DRAIN STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/727287 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8056 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727287 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727287
FinFETs with high quality source/drain structures Oct 5, 2017 Issued
Array ( [id] => 14707389 [patent_doc_number] => 10381457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Transistor with contacted deep well region [patent_app_type] => utility [patent_app_number] => 15/722885 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6150 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/722885
Transistor with contacted deep well region Oct 1, 2017 Issued
Array ( [id] => 13754967 [patent_doc_number] => 10170437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-01 [patent_title] => Via disguise to protect the security product from delayering and graphic design system (GDS) hacking and method for producing the same [patent_app_type] => utility [patent_app_number] => 15/714503 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714503 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714503
Via disguise to protect the security product from delayering and graphic design system (GDS) hacking and method for producing the same Sep 24, 2017 Issued
Array ( [id] => 14366745 [patent_doc_number] => 10304684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Semiconductor device having buried gate structure and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/713798 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 45 [patent_no_of_words] => 22063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713798 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/713798
Semiconductor device having buried gate structure and method for fabricating the same Sep 24, 2017 Issued
Array ( [id] => 12917683 [patent_doc_number] => 20180197737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR MANUFACTURING METHOD AND HIGH ELECTRON MOBILITY TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/713727 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713727 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/713727
High electron mobility transistor manufacturing method and high electron mobility transistor Sep 24, 2017 Issued
Array ( [id] => 14110747 [patent_doc_number] => 20190097049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => REDUCING SERIES RESISTANCE BETWEEN SOURCE AND/OR DRAIN REGIONS AND A CHANNEL REGION [patent_app_type] => utility [patent_app_number] => 15/714491 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714491 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714491
Reducing series resistance between source and/or drain regions and a channel region Sep 24, 2017 Issued
Array ( [id] => 14769383 [patent_doc_number] => 10396093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Three-dimensional semiconductor memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 15/714254 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 13482 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714254 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714254
Three-dimensional semiconductor memory device and method of operating the same Sep 24, 2017 Issued
Array ( [id] => 14110047 [patent_doc_number] => 20190096699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => PACKAGE STRUCTURE AND CHIP STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/713708 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713708 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/713708
Package structure and chip structure Sep 24, 2017 Issued
Array ( [id] => 14110651 [patent_doc_number] => 20190097001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => ELECTRODE STRUCTURE FOR FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/714382 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714382 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714382
ELECTRODE STRUCTURE FOR FIELD EFFECT TRANSISTOR Sep 24, 2017 Abandoned
Array ( [id] => 15475549 [patent_doc_number] => 10553661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Display substrate and display apparatus including the same [patent_app_type] => utility [patent_app_number] => 15/713983 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713983 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/713983
Display substrate and display apparatus including the same Sep 24, 2017 Issued
Array ( [id] => 15109013 [patent_doc_number] => 10475838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Multi-pixel detector and associated method for increasing angular sensitivity [patent_app_type] => utility [patent_app_number] => 15/714502 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4203 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714502 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714502
Multi-pixel detector and associated method for increasing angular sensitivity Sep 24, 2017 Issued
Array ( [id] => 15286485 [patent_doc_number] => 10515912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Integrated circuit packages [patent_app_type] => utility [patent_app_number] => 15/713660 [patent_app_country] => US [patent_app_date] => 2017-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 11886 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713660 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/713660
Integrated circuit packages Sep 23, 2017 Issued
Array ( [id] => 13214759 [patent_doc_number] => 10121755 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-06 [patent_title] => Robust chamfer design for seal ring [patent_app_type] => utility [patent_app_number] => 15/713687 [patent_app_country] => US [patent_app_date] => 2017-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713687 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/713687
Robust chamfer design for seal ring Sep 23, 2017 Issued
Array ( [id] => 14332851 [patent_doc_number] => 10297452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Methods of forming a gate contact structure for a transistor [patent_app_type] => utility [patent_app_number] => 15/712301 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712301 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/712301
Methods of forming a gate contact structure for a transistor Sep 21, 2017 Issued
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