
John B. Vigushin
Examiner (ID: 4424)
| Most Active Art Unit | 2841 |
| Art Unit(s) | 2841, 2103, 2827, 2835, 3662 |
| Total Applications | 656 |
| Issued Applications | 594 |
| Pending Applications | 37 |
| Abandoned Applications | 25 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7603148
[patent_doc_number] => 07235886
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-26
[patent_title] => 'Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby'
[patent_app_type] => utility
[patent_app_number] => 10/023819
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 3067
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/235/07235886.pdf
[firstpage_image] =>[orig_patent_app_number] => 10023819
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/023819 | Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby | Dec 20, 2001 | Issued |
Array
(
[id] => 6078254
[patent_doc_number] => 20020080590
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-27
[patent_title] => 'Printed circuit board arrangement for printed circuits with electronic components'
[patent_app_type] => new
[patent_app_number] => 10/025716
[patent_app_country] => US
[patent_app_date] => 2001-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1859
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0080/20020080590.pdf
[firstpage_image] =>[orig_patent_app_number] => 10025716
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/025716 | Printed circuit board arrangement for printed circuits with electronic components | Dec 17, 2001 | Abandoned |
Array
(
[id] => 6207141
[patent_doc_number] => 20020071260
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-13
[patent_title] => 'Electronic board assembly including two elementary boards each carrying connectors on an edge thereof'
[patent_app_type] => new
[patent_app_number] => 10/016445
[patent_app_country] => US
[patent_app_date] => 2001-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2449
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20020071260.pdf
[firstpage_image] =>[orig_patent_app_number] => 10016445
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/016445 | Electronic board assembly including two elementary boards each carrying connectors on an edge thereof | Dec 9, 2001 | Issued |
Array
(
[id] => 1132554
[patent_doc_number] => 06787895
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-07
[patent_title] => 'Leadless chip carrier for reduced thermal resistance'
[patent_app_type] => B1
[patent_app_number] => 10/013130
[patent_app_country] => US
[patent_app_date] => 2001-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4404
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/787/06787895.pdf
[firstpage_image] =>[orig_patent_app_number] => 10013130
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/013130 | Leadless chip carrier for reduced thermal resistance | Dec 6, 2001 | Issued |
Array
(
[id] => 1418450
[patent_doc_number] => 06535395
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-18
[patent_title] => 'Processor power delivery system'
[patent_app_type] => B2
[patent_app_number] => 10/005464
[patent_app_country] => US
[patent_app_date] => 2001-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2333
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/535/06535395.pdf
[firstpage_image] =>[orig_patent_app_number] => 10005464
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/005464 | Processor power delivery system | Dec 2, 2001 | Issued |
Array
(
[id] => 6627970
[patent_doc_number] => 20030102555
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-05
[patent_title] => 'Electronic assembly with sandwiched capacitors and methods of manufacture'
[patent_app_type] => new
[patent_app_number] => 10/006292
[patent_app_country] => US
[patent_app_date] => 2001-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 11774
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20030102555.pdf
[firstpage_image] =>[orig_patent_app_number] => 10006292
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/006292 | Electronic assembly with sandwiched capacitors and methods of manufacture | Dec 2, 2001 | Issued |
Array
(
[id] => 6636093
[patent_doc_number] => 20030103338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-05
[patent_title] => 'Electronic package having multiple-zone interconnects and methods of manufacture'
[patent_app_type] => new
[patent_app_number] => 10/004002
[patent_app_country] => US
[patent_app_date] => 2001-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6619
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0103/20030103338.pdf
[firstpage_image] =>[orig_patent_app_number] => 10004002
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/004002 | Electronic packages having multiple-zone interconnects and methods of manufacture | Nov 29, 2001 | Issued |
Array
(
[id] => 1299355
[patent_doc_number] => 06627824
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'Support circuit with a tapered through-hole for a semiconductor chip assembly'
[patent_app_type] => B1
[patent_app_number] => 10/002732
[patent_app_country] => US
[patent_app_date] => 2001-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 49
[patent_no_of_words] => 9392
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/627/06627824.pdf
[firstpage_image] =>[orig_patent_app_number] => 10002732
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/002732 | Support circuit with a tapered through-hole for a semiconductor chip assembly | Nov 14, 2001 | Issued |
Array
(
[id] => 5934608
[patent_doc_number] => 20020060906
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-23
[patent_title] => 'Interconnecting method of wiring in printed circuit boards and printed circuit board unit'
[patent_app_type] => new
[patent_app_number] => 10/008841
[patent_app_country] => US
[patent_app_date] => 2001-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2185
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20020060906.pdf
[firstpage_image] =>[orig_patent_app_number] => 10008841
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/008841 | Interconnecting method of wiring in printed circuit boards and printed circuit board unit | Nov 12, 2001 | Issued |
Array
(
[id] => 6207140
[patent_doc_number] => 20020071259
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-13
[patent_title] => 'Circuit board assembly'
[patent_app_type] => new
[patent_app_number] => 09/986645
[patent_app_country] => US
[patent_app_date] => 2001-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1550
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20020071259.pdf
[firstpage_image] =>[orig_patent_app_number] => 09986645
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/986645 | Circuit board assembly | Nov 8, 2001 | Abandoned |
Array
(
[id] => 6094206
[patent_doc_number] => 20020051349
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-02
[patent_title] => 'Structure of drawing out flexible circuit member'
[patent_app_type] => new
[patent_app_number] => 09/984189
[patent_app_country] => US
[patent_app_date] => 2001-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4912
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0051/20020051349.pdf
[firstpage_image] =>[orig_patent_app_number] => 09984189
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/984189 | Structure of drawing out flexible circuit member | Oct 28, 2001 | Issued |
Array
(
[id] => 1360653
[patent_doc_number] => 06576992
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-10
[patent_title] => 'Chip scale stacking system and method'
[patent_app_type] => B1
[patent_app_number] => 10/005581
[patent_app_country] => US
[patent_app_date] => 2001-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 22
[patent_no_of_words] => 7172
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/576/06576992.pdf
[firstpage_image] =>[orig_patent_app_number] => 10005581
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/005581 | Chip scale stacking system and method | Oct 25, 2001 | Issued |
Array
(
[id] => 6584144
[patent_doc_number] => 20020041489
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-11
[patent_title] => 'Semiconductor package with stress inhibiting intermediate mounting substrate'
[patent_app_type] => new
[patent_app_number] => 09/975100
[patent_app_country] => US
[patent_app_date] => 2001-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4057
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20020041489.pdf
[firstpage_image] =>[orig_patent_app_number] => 09975100
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/975100 | Semiconductor package with stress inhibiting intermediate mounting substrate | Oct 9, 2001 | Issued |
Array
(
[id] => 613025
[patent_doc_number] => 07148424
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-12-12
[patent_title] => 'Disposable electronic devices with deconstructable construction and method'
[patent_app_type] => utility
[patent_app_number] => 09/971547
[patent_app_country] => US
[patent_app_date] => 2001-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2733
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/148/07148424.pdf
[firstpage_image] =>[orig_patent_app_number] => 09971547
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/971547 | Disposable electronic devices with deconstructable construction and method | Oct 4, 2001 | Issued |
Array
(
[id] => 6589452
[patent_doc_number] => 20020015291
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-07
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/970668
[patent_app_country] => US
[patent_app_date] => 2001-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 11602
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20020015291.pdf
[firstpage_image] =>[orig_patent_app_number] => 09970668
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/970668 | Semiconductor device | Oct 4, 2001 | Issued |
Array
(
[id] => 6123573
[patent_doc_number] => 20020074653
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'Electronic component overlapping dice of unsingulated semiconductor wafer'
[patent_app_type] => new
[patent_app_number] => 09/971981
[patent_app_country] => US
[patent_app_date] => 2001-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 11786
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20020074653.pdf
[firstpage_image] =>[orig_patent_app_number] => 09971981
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/971981 | Electronic component overlapping dice of unsingulated semiconductor wafer | Oct 3, 2001 | Issued |
Array
(
[id] => 1216009
[patent_doc_number] => 06711027
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-23
[patent_title] => 'Modules having paths of different impedances'
[patent_app_type] => B2
[patent_app_number] => 09/971947
[patent_app_country] => US
[patent_app_date] => 2001-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 47
[patent_no_of_words] => 12232
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/711/06711027.pdf
[firstpage_image] =>[orig_patent_app_number] => 09971947
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/971947 | Modules having paths of different impedances | Oct 3, 2001 | Issued |
Array
(
[id] => 6773179
[patent_doc_number] => 20030016517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-23
[patent_title] => 'Systems having modules with on die terminations'
[patent_app_type] => new
[patent_app_number] => 09/970442
[patent_app_country] => US
[patent_app_date] => 2001-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 12380
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0016/20030016517.pdf
[firstpage_image] =>[orig_patent_app_number] => 09970442
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/970442 | Systems having modules with on die terminations | Oct 3, 2001 | Issued |
Array
(
[id] => 1395660
[patent_doc_number] => 06560122
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-05-06
[patent_title] => 'Chip package with molded underfill'
[patent_app_type] => B2
[patent_app_number] => 09/967676
[patent_app_country] => US
[patent_app_date] => 2001-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 5288
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/560/06560122.pdf
[firstpage_image] =>[orig_patent_app_number] => 09967676
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/967676 | Chip package with molded underfill | Sep 27, 2001 | Issued |
Array
(
[id] => 6812121
[patent_doc_number] => 20030071671
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-17
[patent_title] => 'Topology for flexible and precise signal timing adjustment'
[patent_app_type] => new
[patent_app_number] => 09/966649
[patent_app_country] => US
[patent_app_date] => 2001-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6122
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20030071671.pdf
[firstpage_image] =>[orig_patent_app_number] => 09966649
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/966649 | Topology for flexible and precise signal timing adjustment | Sep 27, 2001 | Issued |