Search

John C. Hong

Examiner (ID: 4091, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19878571 [patent_doc_number] => 20250110828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => METHOD AND APPARATUS FOR PERFORMING DATA ACCESS CONTROL OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/882713 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882713
METHOD AND APPARATUS FOR PERFORMING DATA ACCESS CONTROL OF MEMORY DEVICE Sep 10, 2024 Pending
Array ( [id] => 19686335 [patent_doc_number] => 20250004880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/882152 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882152
MEMORY SYSTEM Sep 10, 2024 Pending
Array ( [id] => 19660599 [patent_doc_number] => 20240427664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => ERROR RATES FOR MEMORY WITH BUILT IN ERROR CORRECTION AND DETECTION [patent_app_type] => utility [patent_app_number] => 18/825345 [patent_app_country] => US [patent_app_date] => 2024-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18825345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/825345
ERROR RATES FOR MEMORY WITH BUILT IN ERROR CORRECTION AND DETECTION Sep 4, 2024 Pending
Array ( [id] => 19645024 [patent_doc_number] => 20240419544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => Reduction of Errors in Data Retrieved from a Memory Device to Apply an Error Correction Code of a Predetermined Code Rate [patent_app_type] => utility [patent_app_number] => 18/821886 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821886 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821886
Reduction of Errors in Data Retrieved from a Memory Device to Apply an Error Correction Code of a Predetermined Code Rate Aug 29, 2024 Pending
Array ( [id] => 19620240 [patent_doc_number] => 20240405920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => INFORMATION PROCESSING APPARATUS, COMMUNICATION SYSTEM, INFORMATION PROCESSING METHOD AND PROGRAM [patent_app_type] => utility [patent_app_number] => 18/806709 [patent_app_country] => US [patent_app_date] => 2024-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18806709 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/806709
INFORMATION PROCESSING APPARATUS, COMMUNICATION SYSTEM, INFORMATION PROCESSING METHOD AND PROGRAM Aug 15, 2024 Pending
Array ( [id] => 19603094 [patent_doc_number] => 20240393974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => AUTHENTICATED STATELESS MOUNT STRING FOR A DISTRIBUTED FILE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/795647 [patent_app_country] => US [patent_app_date] => 2024-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18795647 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/795647
AUTHENTICATED STATELESS MOUNT STRING FOR A DISTRIBUTED FILE SYSTEM Aug 5, 2024 Pending
Array ( [id] => 19588371 [patent_doc_number] => 20240385928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => DEEP NEURAL NETWORK IMPLEMENTATION FOR SOFT DECODING OF BCH CODE [patent_app_type] => utility [patent_app_number] => 18/787270 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787270 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/787270
DEEP NEURAL NETWORK IMPLEMENTATION FOR SOFT DECODING OF BCH CODE Jul 28, 2024 Pending
Array ( [id] => 20408864 [patent_doc_number] => 20250377973 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2025-12-11 [patent_title] => DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/777165 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/777165
DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES Jul 17, 2024 Pending
Array ( [id] => 20408864 [patent_doc_number] => 20250377973 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2025-12-11 [patent_title] => DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/777165 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/777165
DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES Jul 17, 2024 Pending
Array ( [id] => 19985703 [patent_doc_number] => 20250123925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => PAGE-BY-PAGE LEVEL SHAPING [patent_app_type] => utility [patent_app_number] => 18/774464 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774464
PAGE-BY-PAGE LEVEL SHAPING Jul 15, 2024 Pending
Array ( [id] => 20061686 [patent_doc_number] => 20250199908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => METHOD AND SYSTEM FOR ON-ASIC ERROR CONTROL ENCODING [patent_app_type] => utility [patent_app_number] => 18/772604 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772604 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772604
METHOD AND SYSTEM FOR ON-ASIC ERROR CONTROL ENCODING Jul 14, 2024 Pending
Array ( [id] => 19878569 [patent_doc_number] => 20250110826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => VALLEY SEARCH IN READ ERROR RECOVERY FOR A MEMORY DEVICE USING LOW-DENSITY PARITY CHECK SYNDROME WEIGHT AND AUTO-READ CALIBRATION [patent_app_type] => utility [patent_app_number] => 18/771829 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771829 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771829
VALLEY SEARCH IN READ ERROR RECOVERY FOR A MEMORY DEVICE USING LOW-DENSITY PARITY CHECK SYNDROME WEIGHT AND AUTO-READ CALIBRATION Jul 11, 2024 Pending
Array ( [id] => 19978805 [patent_doc_number] => 12346280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Multi-port media access channel (MAC) with flexible data-path width [patent_app_type] => utility [patent_app_number] => 18/770975 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 2157 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770975 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770975
Multi-port media access channel (MAC) with flexible data-path width Jul 11, 2024 Issued
Array ( [id] => 20482654 [patent_doc_number] => 12531130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Non-volatile storage device offloading [patent_app_type] => utility [patent_app_number] => 18/758495 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758495 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758495
Non-volatile storage device offloading Jun 27, 2024 Issued
Array ( [id] => 20027117 [patent_doc_number] => 20250165339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => MEMORY CONTROLLER MANAGING READ LEVEL INFORMATION, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/753410 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753410 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753410
Memory controller managing read level information, memory system including the same, and operating method of the memory controller Jun 24, 2024 Issued
Array ( [id] => 19686329 [patent_doc_number] => 20250004874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => METHOD FOR ACCESSING A DATA BLOCK, STORED IN A MEMORY UNIT OF A COMPUTING UNIT, OF A NUMBER OF DATA BLOCKS [patent_app_type] => utility [patent_app_number] => 18/749984 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749984
Method for accessing a data block, stored in a memory unit of a computing unit, of a number of data blocks Jun 20, 2024 Issued
Array ( [id] => 19645016 [patent_doc_number] => 20240419536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => MEMORY CONTROLLER AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/743554 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743554 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743554
MEMORY CONTROLLER AND MEMORY SYSTEM Jun 13, 2024 Pending
Array ( [id] => 19466417 [patent_doc_number] => 20240320087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Data Error Correction Method and Apparatus, Memory Controller, and System [patent_app_type] => utility [patent_app_number] => 18/735483 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735483 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735483
Data Error Correction Method and Apparatus, Memory Controller, and System Jun 5, 2024 Pending
Array ( [id] => 20123284 [patent_doc_number] => 20250238315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => SEMICONDUCTOR MEMORY APPARATUS CONFIGURED TO PERFORM AN ERROR CHECK [patent_app_type] => utility [patent_app_number] => 18/733308 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733308
SEMICONDUCTOR MEMORY APPARATUS CONFIGURED TO PERFORM AN ERROR CHECK Jun 3, 2024 Pending
Array ( [id] => 20395380 [patent_doc_number] => 20250370855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => ENFORCED CHECKSUMS FOR HUMAN READABLE PRIME NUMBER COMPRESSION (HRPNC) [patent_app_type] => utility [patent_app_number] => 18/678360 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/678360
ENFORCED CHECKSUMS FOR HUMAN READABLE PRIME NUMBER COMPRESSION (HRPNC) May 29, 2024 Pending
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