Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17223796 [patent_doc_number] => 11176298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-16 [patent_title] => Method for modeling [patent_app_type] => utility [patent_app_number] => 17/221265 [patent_app_country] => US [patent_app_date] => 2021-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3431 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/221265
Method for modeling Apr 1, 2021 Issued
Array ( [id] => 16951591 [patent_doc_number] => 20210210283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => WIRELESS CHARGING COIL AND TERMINAL DEVICE [patent_app_type] => utility [patent_app_number] => 17/211913 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211913
Wireless charging coil and terminal device Mar 24, 2021 Issued
Array ( [id] => 17637189 [patent_doc_number] => 11347913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-31 [patent_title] => Method of reconstruction of post-layout design for graphical display [patent_app_type] => utility [patent_app_number] => 17/207306 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207306
Method of reconstruction of post-layout design for graphical display Mar 18, 2021 Issued
Array ( [id] => 19369158 [patent_doc_number] => 12061237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Detecting whether a battery management system is abnormal [patent_app_type] => utility [patent_app_number] => 17/204759 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/204759
Detecting whether a battery management system is abnormal Mar 16, 2021 Issued
Array ( [id] => 17786806 [patent_doc_number] => 11409931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-09 [patent_title] => Systems and methods for optimizing scan pipelining in hierarchical test design [patent_app_type] => utility [patent_app_number] => 17/203497 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203497 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203497
Systems and methods for optimizing scan pipelining in hierarchical test design Mar 15, 2021 Issued
Array ( [id] => 17861931 [patent_doc_number] => 11443089 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-13 [patent_title] => Timing verification of non-standard library blocks [patent_app_type] => utility [patent_app_number] => 17/249833 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7777 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/249833
Timing verification of non-standard library blocks Mar 14, 2021 Issued
Array ( [id] => 19493397 [patent_doc_number] => 12112113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Complementary die-to-die interface [patent_app_type] => utility [patent_app_number] => 17/194003 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194003
Complementary die-to-die interface Mar 4, 2021 Issued
Array ( [id] => 17069582 [patent_doc_number] => 20210271798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => MAIN BOARD WITH INTEGRATED TRUSTED PLATFORM MODULE FOR A COMPUTER DEVICE AND METHOD FOR PRODUCING A MAIN BOARD WITH INTEGRATED TRUSTED PLATFORM MODULE [patent_app_type] => utility [patent_app_number] => 17/186415 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186415
Main board with integrated trusted platform module for a computer device and method for producing a main board with integrated trusted platform module Feb 25, 2021 Issued
Array ( [id] => 19703114 [patent_doc_number] => 12197138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Machine learning on overlay management [patent_app_type] => utility [patent_app_number] => 17/185827 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185827 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185827
Machine learning on overlay management Feb 24, 2021 Issued
Array ( [id] => 16903551 [patent_doc_number] => 20210182467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 17/184940 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184940 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184940
Integrated circuit design method, system and computer program product Feb 24, 2021 Issued
Array ( [id] => 17053971 [patent_doc_number] => 20210263405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => INCLUSION OF STOCHASTIC BEHAVIOR IN SOURCE MASK OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 17/183291 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/183291
Inclusion of stochastic behavior in source mask optimization Feb 22, 2021 Issued
Array ( [id] => 17053970 [patent_doc_number] => 20210263404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => STOCHASTIC SIGNAL PREDICTION IN COMPACT MODELING [patent_app_type] => utility [patent_app_number] => 17/182135 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182135 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182135
Stochastic signal prediction in compact modeling Feb 21, 2021 Issued
Array ( [id] => 17039554 [patent_doc_number] => 20210256190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => METHOD, COMPUTER-BASED SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PLANNING PARTITIONS FOR A PROGRAMMABLE GATE ARRAY [patent_app_type] => utility [patent_app_number] => 17/178787 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178787
Method, computer-based system and computer program product for planning partitions for a programmable gate array Feb 17, 2021 Issued
Array ( [id] => 18297870 [patent_doc_number] => 20230107556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => MACHINE LEARNING BASED SUBRESOLUTION ASSIST FEATURE PLACEMENT [patent_app_type] => utility [patent_app_number] => 17/907756 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17907756 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/907756
Machine learning based subresolution assist feature placement Feb 11, 2021 Issued
Array ( [id] => 20563761 [patent_doc_number] => 12566368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Method for determining a mask pattern comprising optical proximity corrections using a trained machine learning model [patent_app_type] => utility [patent_app_number] => 17/796751 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 20524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17796751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/796751
Method for determining a mask pattern comprising optical proximity corrections using a trained machine learning model Feb 3, 2021 Issued
Array ( [id] => 17380191 [patent_doc_number] => 11238208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Methods for optical proximity correction and methods of fabricating semiconductor device using the same [patent_app_type] => utility [patent_app_number] => 17/157229 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 60 [patent_no_of_words] => 13237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157229
Methods for optical proximity correction and methods of fabricating semiconductor device using the same Jan 24, 2021 Issued
Array ( [id] => 17515901 [patent_doc_number] => 11295056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Vertex-based OPC for opening patterning [patent_app_type] => utility [patent_app_number] => 17/144975 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 39 [patent_no_of_words] => 12232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144975
Vertex-based OPC for opening patterning Jan 7, 2021 Issued
Array ( [id] => 17017425 [patent_doc_number] => 11087067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Systems and methods for implementing tile-level predication within a machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 17/142314 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13941 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142314
Systems and methods for implementing tile-level predication within a machine perception and dense algorithm integrated circuit Jan 5, 2021 Issued
Array ( [id] => 18527950 [patent_doc_number] => 11714944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Optimization of physical cell placement for integrated circuits [patent_app_type] => utility [patent_app_number] => 17/139016 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 9310 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139016
Optimization of physical cell placement for integrated circuits Dec 30, 2020 Issued
Array ( [id] => 16950587 [patent_doc_number] => 20210209279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => CONVERGENCE CENTRIC COVERAGE FOR CLOCK DOMAIN CROSSING (CDC) JITTER IN SIMULATION [patent_app_type] => utility [patent_app_number] => 17/139915 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139915 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139915
Convergence centric coverage for clock domain crossing (CDC) jitter in simulation Dec 30, 2020 Issued
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