John C. Hong

Array ( [id] => 19228795 [patent_doc_number] => 12008433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Variational quantum state preparation [patent_app_type] => utility [patent_app_number] => 16/967339 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5478 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16967339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15091039 [patent_doc_number] => 20190340330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Method for Integrated Circuit Manufacturing [patent_app_type] => utility [patent_app_number] => 16/516853 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17106554 [patent_doc_number] => 11126772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => Tools and methods for designing a circuit, and circuits made thereby [patent_app_type] => utility [patent_app_number] => 16/511541 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 11675 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16385509 [patent_doc_number] => 10810348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Constructing colorable wiring layouts with wide wires and sandwich rules [patent_app_type] => utility [patent_app_number] => 16/511884 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16535553 [patent_doc_number] => 10878154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Evaluation of nets for suitability of time domain multiplexing during partitioning and placing a circuit design [patent_app_type] => utility [patent_app_number] => 16/510600 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4477 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17056416 [patent_doc_number] => 20210265850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => MANAGEMENT SERVER, MANAGEMENT SYSTEM, AND MANAGEMENT METHOD [patent_app_type] => utility [patent_app_number] => 17/256174 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17256174 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16338444 [patent_doc_number] => 10789404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-29 [patent_title] => System, method, and computer program product for generating a formal verification model [patent_app_type] => utility [patent_app_number] => 16/434129 [patent_app_country] => US [patent_app_date] => 2019-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16434129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16355557 [patent_doc_number] => 10796069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-06 [patent_title] => Bump connection placement in quantum devices in a flip chip configuration [patent_app_type] => utility [patent_app_number] => 16/433253 [patent_app_country] => US [patent_app_date] => 2019-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16433253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16431885 [patent_doc_number] => 10831971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Net layer promotion with swap capability in electronic design [patent_app_type] => utility [patent_app_number] => 16/431974 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 9895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16463108 [patent_doc_number] => 10846457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Lithography system, simulation apparatus, and pattern forming method [patent_app_type] => utility [patent_app_number] => 16/431221 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 17118 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18890922 [patent_doc_number] => 11869699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Inductive energy emitter/receiver for an inductive charger of an electric vehicle [patent_app_type] => utility [patent_app_number] => 17/057335 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3606 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17057335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16921171 [patent_doc_number] => 20210194263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => ENERGY STORAGE APPARATUS, EXTERNAL DISCHARGE DEVICE, AND DISCHARGE METHOD OF ENERGY STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/056996 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17056996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14751199 [patent_doc_number] => 20190258773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => Method and System for Determining Circuit Failure Rate [patent_app_type] => utility [patent_app_number] => 16/404678 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17757547 [patent_doc_number] => 11397840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-26 [patent_title] => Edge placement errors for optical lithography [patent_app_type] => utility [patent_app_number] => 16/353888 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 8106 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17365226 [patent_doc_number] => 11232249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Method for determining curvilinear patterns for patterning device [patent_app_type] => utility [patent_app_number] => 16/976492 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 13871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16976492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17223798 [patent_doc_number] => 11176300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Systems and methods for creating individualized processing chips and assemblies [patent_app_type] => utility [patent_app_number] => 16/266043 [patent_app_country] => US [patent_app_date] => 2019-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 23052 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16447202 [patent_doc_number] => 10839131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Three-dimensional mask model for photolithography simulation [patent_app_type] => utility [patent_app_number] => 16/265367 [patent_app_country] => US [patent_app_date] => 2019-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 12953 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16265367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19327867 [patent_doc_number] => 12045555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Method to label substrates based on process parameters [patent_app_type] => utility [patent_app_number] => 16/960376 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 14563 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16960376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16987215 [patent_doc_number] => 11074391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips [patent_app_type] => utility [patent_app_number] => 16/253812 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10515 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16253812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15653199 [patent_doc_number] => 20200089130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => Optical Mode Optimization for Wafer Inspection [patent_app_type] => utility [patent_app_number] => 16/250128 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250128 [rel_patent_id] =>[rel_patent_doc_number] =>)