Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16433414 [patent_doc_number] => 10833517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Charging device for vehicle, vehicle, and method for controlling the vehicle [patent_app_type] => utility [patent_app_number] => 16/180654 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6885 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16180654 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/180654
Charging device for vehicle, vehicle, and method for controlling the vehicle Nov 4, 2018 Issued
Array ( [id] => 16036041 [patent_doc_number] => 10680455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Demand charge minimization in behind-the-meter energy management systems [patent_app_type] => utility [patent_app_number] => 16/180415 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16180415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/180415
Demand charge minimization in behind-the-meter energy management systems Nov 4, 2018 Issued
Array ( [id] => 17231006 [patent_doc_number] => 20210357563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => SIGNAL INTEGRITY SIMULATION METHOD FOR ENCRYPTION HYBRID MODEL [patent_app_type] => utility [patent_app_number] => 16/493266 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16493266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/493266
Signal integrity simulation method for encryption hybrid model Oct 25, 2018 Issued
Array ( [id] => 15367775 [patent_doc_number] => 20200019652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => INTEGRATED CIRCUIT DESIGN MODEL SPLITTING FOR FORMAL VERIFICATION [patent_app_type] => utility [patent_app_number] => 16/035212 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035212
Integrated circuit design model splitting for formal verification Jul 12, 2018 Issued
Array ( [id] => 16232971 [patent_doc_number] => 10740523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-11 [patent_title] => Systems and methods for providing defect recovery in an integrated circuit [patent_app_type] => utility [patent_app_number] => 16/034019 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16034019 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/034019
Systems and methods for providing defect recovery in an integrated circuit Jul 11, 2018 Issued
Array ( [id] => 15367801 [patent_doc_number] => 20200019665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => CELL PLACEMENT IN A CIRCUIT WITH SHARED INPUTS AND OUTPUTS [patent_app_type] => utility [patent_app_number] => 16/033412 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033412
Cell placement in a circuit with shared inputs and outputs Jul 11, 2018 Issued
Array ( [id] => 15367779 [patent_doc_number] => 20200019654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => VERIFICATION ALGORITHM ENGINE SELECTION [patent_app_type] => utility [patent_app_number] => 16/033417 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033417 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033417
Verification algorithm engine selection Jul 11, 2018 Issued
Array ( [id] => 16485429 [patent_doc_number] => 20200379032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => A METHOD AND A CIRCUIT FOR ADAPTIVE REGULATION OF BODY BIAS VOLTAGES CONTROLLING NMOS AND PMOS TRANSISTORS OF AN IC [patent_app_type] => utility [patent_app_number] => 16/635780 [patent_app_country] => US [patent_app_date] => 2018-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16635780 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/635780
Method and a circuit for adaptive regulation of body bias voltages controlling NMOS and PMOS transistors of an IC Jul 10, 2018 Issued
Array ( [id] => 17066707 [patent_doc_number] => 20210268922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => CONTACTLESS ELECTRICITY SUPPLY SYSTEM FOR VEHICLE [patent_app_type] => utility [patent_app_number] => 17/256425 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17256425 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/256425
Contactless electricity supply system for vehicle Jun 28, 2018 Issued
Array ( [id] => 15731521 [patent_doc_number] => 10614191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-07 [patent_title] => Performing placement and routing concurrently [patent_app_type] => utility [patent_app_number] => 15/991791 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 11276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991791
Performing placement and routing concurrently May 28, 2018 Issued
Array ( [id] => 13580387 [patent_doc_number] => 20180341742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => FULL-CUSTOM VOLTAGE-DEPENDENT DESIGN RULES (VDRC) FLOW [patent_app_type] => utility [patent_app_number] => 15/989929 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -52 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989929 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989929
Full-custom voltage-dependent design rules (VDRC) flow May 24, 2018 Issued
Array ( [id] => 16146247 [patent_doc_number] => 10706195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => System, method, and computer program product for over-constraint/deadcode detection in a formal verification [patent_app_type] => utility [patent_app_number] => 15/989469 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989469 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989469
System, method, and computer program product for over-constraint/deadcode detection in a formal verification May 24, 2018 Issued
Array ( [id] => 15855461 [patent_doc_number] => 10643018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => System and method for determining return path quality in an electrical circuit [patent_app_type] => utility [patent_app_number] => 15/989393 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5362 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989393 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989393
System and method for determining return path quality in an electrical circuit May 24, 2018 Issued
Array ( [id] => 15232265 [patent_doc_number] => 10503857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Computer executing method, clock data processing system and computer readable storage medium [patent_app_type] => utility [patent_app_number] => 15/956757 [patent_app_country] => US [patent_app_date] => 2018-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15956757 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/956757
Computer executing method, clock data processing system and computer readable storage medium Apr 18, 2018 Issued
Array ( [id] => 16263573 [patent_doc_number] => 10755009 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-25 [patent_title] => Optimization after allocating potential slacks to clock arrival times [patent_app_type] => utility [patent_app_number] => 15/957710 [patent_app_country] => US [patent_app_date] => 2018-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7415 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15957710 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/957710
Optimization after allocating potential slacks to clock arrival times Apr 18, 2018 Issued
Array ( [id] => 17715654 [patent_doc_number] => 11379647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Multilayer optical proximity correction (OPC) model for OPC correction [patent_app_type] => utility [patent_app_number] => 16/771172 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7799 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16771172 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/771172
Multilayer optical proximity correction (OPC) model for OPC correction Mar 29, 2018 Issued
Array ( [id] => 16543734 [patent_doc_number] => 20200410149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/978968 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16978968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/978968
HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM Mar 25, 2018 Abandoned
Array ( [id] => 13306459 [patent_doc_number] => 20180204766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD [patent_app_type] => utility [patent_app_number] => 15/919652 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919652 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919652
Semiconductor device and semiconductor device fabrication method Mar 12, 2018 Issued
Array ( [id] => 15609901 [patent_doc_number] => 10586014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-10 [patent_title] => Method and system for verification using combined verification data [patent_app_type] => utility [patent_app_number] => 15/915365 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5716 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/915365
Method and system for verification using combined verification data Mar 7, 2018 Issued
Array ( [id] => 12915199 [patent_doc_number] => 20180196909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same [patent_app_type] => utility [patent_app_number] => 15/913819 [patent_app_country] => US [patent_app_date] => 2018-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15913819 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/913819
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same Mar 5, 2018 Abandoned
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