Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16535556 [patent_doc_number] => 10878157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Variant cell height integrated circuit design [patent_app_type] => utility [patent_app_number] => 15/908785 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15908785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/908785
Variant cell height integrated circuit design Feb 27, 2018 Issued
Array ( [id] => 14689641 [patent_doc_number] => 20190243936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => Electronic design tools using non-synthesizable circuit elements [patent_app_type] => utility [patent_app_number] => 15/891395 [patent_app_country] => US [patent_app_date] => 2018-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15891395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/891395
Electronic design tools using non-synthesizable circuit elements Feb 7, 2018 Issued
Array ( [id] => 15855327 [patent_doc_number] => 10642950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Verifying planarization performance using electrical measures [patent_app_type] => utility [patent_app_number] => 15/889415 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7416 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889415 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/889415
Verifying planarization performance using electrical measures Feb 5, 2018 Issued
Array ( [id] => 15731525 [patent_doc_number] => 10614193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Power mode-based operational capability-aware code coverage [patent_app_type] => utility [patent_app_number] => 15/885098 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6374 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885098 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885098
Power mode-based operational capability-aware code coverage Jan 30, 2018 Issued
Array ( [id] => 15373931 [patent_doc_number] => 10528686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Clock jitter emulation [patent_app_type] => utility [patent_app_number] => 15/863566 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863566 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/863566
Clock jitter emulation Jan 4, 2018 Issued
Array ( [id] => 17106559 [patent_doc_number] => 11126777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Layout routing structure and layout routing method for improving SI performance of signal [patent_app_type] => utility [patent_app_number] => 16/097235 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3093 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16097235 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/097235
Layout routing structure and layout routing method for improving SI performance of signal Nov 29, 2017 Issued
Array ( [id] => 12592533 [patent_doc_number] => 20180089340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => INTEGRATED CIRCUIT DESIGN USING GENERATION AND INSTANTIATION OF CIRCUIT STENCILS [patent_app_type] => utility [patent_app_number] => 15/809869 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809869 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/809869
Integrated circuit design using generation and instantiation of circuit stencils Nov 9, 2017 Issued
Array ( [id] => 12689287 [patent_doc_number] => 20180121595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => APPLYING RANDOM NETS CREDIT IN AN EFFICIENT STATIC TIMING ANALYSIS [patent_app_type] => utility [patent_app_number] => 15/801749 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6616 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801749 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/801749
APPLYING RANDOM NETS CREDIT IN AN EFFICIENT STATIC TIMING ANALYSIS Nov 1, 2017 Abandoned
Array ( [id] => 15232259 [patent_doc_number] => 10503854 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-10 [patent_title] => Method and system for generating validation tests [patent_app_type] => utility [patent_app_number] => 15/725307 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4034 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/725307
Method and system for generating validation tests Oct 4, 2017 Issued
Array ( [id] => 16033099 [patent_doc_number] => 10678973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Machine-learning design enablement platform [patent_app_type] => utility [patent_app_number] => 15/724663 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724663 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724663
Machine-learning design enablement platform Oct 3, 2017 Issued
Array ( [id] => 14136223 [patent_doc_number] => 20190102501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => Simulation-Assisted Wafer Rework Determination [patent_app_type] => utility [patent_app_number] => 15/725219 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/725219
Simulation-assisted wafer rework determination Oct 3, 2017 Issued
Array ( [id] => 15198567 [patent_doc_number] => 10496780 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-03 [patent_title] => Dynamic model generation for lithographic simulation [patent_app_type] => utility [patent_app_number] => 15/724264 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 10112 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724264 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724264
Dynamic model generation for lithographic simulation Oct 2, 2017 Issued
Array ( [id] => 13318911 [patent_doc_number] => 20180210993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => BLOCK-LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS [patent_app_type] => utility [patent_app_number] => 15/723308 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723308
Block-level design method for heterogeneous PG-structure cells Oct 2, 2017 Issued
Array ( [id] => 15075759 [patent_doc_number] => 10467370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-05 [patent_title] => Methods, systems, and computer program product for implementing a net as a transmission line model in a schematic driven extracted view for an electronic design [patent_app_type] => utility [patent_app_number] => 15/721851 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721851 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721851
Methods, systems, and computer program product for implementing a net as a transmission line model in a schematic driven extracted view for an electronic design Sep 29, 2017 Issued
Array ( [id] => 16033109 [patent_doc_number] => 10678978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-09 [patent_title] => Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view [patent_app_type] => utility [patent_app_number] => 15/721853 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721853 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721853
Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view Sep 29, 2017 Issued
Array ( [id] => 15486859 [patent_doc_number] => 10558780 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-11 [patent_title] => Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design [patent_app_type] => utility [patent_app_number] => 15/721845 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 12893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721845 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721845
Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design Sep 29, 2017 Issued
Array ( [id] => 16409086 [patent_doc_number] => 10817641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-27 [patent_title] => Method and system to implement topology integrity throughout routing implementations [patent_app_type] => utility [patent_app_number] => 15/721655 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721655
Method and system to implement topology integrity throughout routing implementations Sep 28, 2017 Issued
Array ( [id] => 13707335 [patent_doc_number] => 20170364622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => SIMULATING EFFECTS OF TEMPERATURE ON ACOUSTIC MICROWAVE FILTERS [patent_app_type] => utility [patent_app_number] => 15/695393 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695393 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695393
Simulating effects of temperature on acoustic microwave filters Sep 4, 2017 Issued
Array ( [id] => 12062344 [patent_doc_number] => 20170338688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'WIRELESS CHARGING APPARATUS AND WIRELESS CHARGING METHOD' [patent_app_type] => utility [patent_app_number] => 15/670774 [patent_app_country] => US [patent_app_date] => 2017-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5913 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15670774 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/670774
Wireless charging apparatus and wireless charging method Aug 6, 2017 Issued
Array ( [id] => 14444227 [patent_doc_number] => 20190179987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => Activity Coverage Assessment of Circuit Designs Under Test Stimuli [patent_app_type] => utility [patent_app_number] => 16/321929 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16321929 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/321929
Activity coverage assessment of circuit designs under test stimuli Jul 30, 2017 Issued
Menu