
John C. Hong
Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )
| Most Active Art Unit | 3726 |
| Art Unit(s) | 3726 |
| Total Applications | 2343 |
| Issued Applications | 1904 |
| Pending Applications | 53 |
| Abandoned Applications | 396 |
Applications
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|---|---|---|---|
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