Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11854949 [patent_doc_number] => 20170229441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'Integrated Circuit Cell Library for Multiple Patterning' [patent_app_type] => utility [patent_app_number] => 15/497103 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9587 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497103 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/497103
Integrated circuit cell library for multiple patterning Apr 24, 2017 Issued
Array ( [id] => 14543583 [patent_doc_number] => 20190207413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => INFORMATION PROCESSING SYSTEM, BATTERY MODULE, CONTROL METHOD, AND PROGRAM [patent_app_type] => utility [patent_app_number] => 16/311864 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16311864 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/311864
Information processing system, battery module, control method, and program Apr 12, 2017 Issued
Array ( [id] => 15467581 [patent_doc_number] => 10549651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Mobile body and mobile body system [patent_app_type] => utility [patent_app_number] => 16/098892 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 8978 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16098892 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/098892
Mobile body and mobile body system Feb 27, 2017 Issued
Array ( [id] => 11945265 [patent_doc_number] => 20170249416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'Integrated Circuit Design Using Generation and Instantiation of Circuit Stencils' [patent_app_type] => utility [patent_app_number] => 15/442338 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12608 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442338 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442338
Integrated circuit design using generation and instantiation of circuit stencils Feb 23, 2017 Issued
Array ( [id] => 11939986 [patent_doc_number] => 20170244135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'POWER STORAGE DEVICE AND POWER STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/432337 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 24608 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432337 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432337
Power storage device and power storage system Feb 13, 2017 Issued
Array ( [id] => 13364799 [patent_doc_number] => 20180233940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => MULTI-AXIS POWER COUPLING [patent_app_type] => utility [patent_app_number] => 15/432796 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432796 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432796
MULTI-AXIS POWER COUPLING Feb 13, 2017 Abandoned
Array ( [id] => 11990683 [patent_doc_number] => 20170294838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'DC-DC VOLTAGE CONVERSION DEVICE' [patent_app_type] => utility [patent_app_number] => 15/431913 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13666 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431913 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431913
DC-DC voltage conversion device Feb 13, 2017 Issued
Array ( [id] => 13364777 [patent_doc_number] => 20180233929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => BATTERY TO BATTERY CHARGER USING ASYMMETRIC BATTERIES [patent_app_type] => utility [patent_app_number] => 15/431324 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431324 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431324
BATTERY TO BATTERY CHARGER USING ASYMMETRIC BATTERIES Feb 12, 2017 Abandoned
Array ( [id] => 12897985 [patent_doc_number] => 20180191170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => CHARGING SYSTEM [patent_app_type] => utility [patent_app_number] => 15/431191 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431191
CHARGING SYSTEM Feb 12, 2017 Abandoned
Array ( [id] => 13830855 [patent_doc_number] => 20190018912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => Decoding-Based Method for Quantum Circuit Optimization [patent_app_type] => utility [patent_app_number] => 16/070309 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/070309
Decoding-based method for quantum circuit optimization Jan 24, 2017 Issued
Array ( [id] => 16949159 [patent_doc_number] => 20210207850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => SOLAR INTEGRATED CHILLER METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/071332 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16071332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/071332
SOLAR INTEGRATED CHILLER METHOD AND SYSTEM Jan 23, 2017 Abandoned
Array ( [id] => 11622158 [patent_doc_number] => 20170132345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'Dynamically Loaded System-Level Simulation' [patent_app_type] => utility [patent_app_number] => 15/406555 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15406555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/406555
Dynamically loaded system-level simulation Jan 12, 2017 Issued
Array ( [id] => 11629896 [patent_doc_number] => 20170140085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SIMULATING EFFECTS OF TEMPERATURE ON ACOUSTIC MICROWAVE FILTERS' [patent_app_type] => utility [patent_app_number] => 15/379850 [patent_app_country] => US [patent_app_date] => 2016-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15379850 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/379850
SIMULATING EFFECTS OF TEMPERATURE ON ACOUSTIC MICROWAVE FILTERS Dec 14, 2016 Abandoned
Array ( [id] => 11637160 [patent_doc_number] => 09659135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Logic structure aware circuit routing' [patent_app_type] => utility [patent_app_number] => 15/372438 [patent_app_country] => US [patent_app_date] => 2016-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4129 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15372438 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/372438
Logic structure aware circuit routing Dec 7, 2016 Issued
Array ( [id] => 11659311 [patent_doc_number] => 09672314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Logic structure aware circuit routing' [patent_app_type] => utility [patent_app_number] => 15/372455 [patent_app_country] => US [patent_app_date] => 2016-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4131 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15372455 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/372455
Logic structure aware circuit routing Dec 7, 2016 Issued
Array ( [id] => 16171834 [patent_doc_number] => 10713406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Multi-die IC layout methods with awareness of mix and match die integration [patent_app_type] => utility [patent_app_number] => 15/778786 [patent_app_country] => US [patent_app_date] => 2016-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9817 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15778786 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/778786
Multi-die IC layout methods with awareness of mix and match die integration Nov 28, 2016 Issued
Array ( [id] => 13292117 [patent_doc_number] => 10157254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Techniques based on electromigration characteristics of cell interconnect [patent_app_type] => utility [patent_app_number] => 15/361970 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 8483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361970 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/361970
Techniques based on electromigration characteristics of cell interconnect Nov 27, 2016 Issued
Array ( [id] => 13292111 [patent_doc_number] => 10157251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Method and system for partitioning circuit cells [patent_app_type] => utility [patent_app_number] => 15/353872 [patent_app_country] => US [patent_app_date] => 2016-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15353872 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/353872
Method and system for partitioning circuit cells Nov 16, 2016 Issued
Array ( [id] => 12736174 [patent_doc_number] => 20180137225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => METHOD AND SYSTEM FOR BUILDING A CELL LIBRARY WITH SEGMENTED TIMING ARC DELAY MODEL [patent_app_type] => utility [patent_app_number] => 15/351771 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/351771
METHOD AND SYSTEM FOR BUILDING A CELL LIBRARY WITH SEGMENTED TIMING ARC DELAY MODEL Nov 14, 2016 Abandoned
Array ( [id] => 11982434 [patent_doc_number] => 20170286589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'System and Method for Defining Care Areas in Repeating Structures of Design Data' [patent_app_type] => utility [patent_app_number] => 15/351813 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351813 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/351813
System and method for defining care areas in repeating structures of design data Nov 14, 2016 Issued
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