Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13402907 [patent_doc_number] => 20180252996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => OPTICAL PROXIMITY CORRECTION METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 15/756799 [patent_app_country] => US [patent_app_date] => 2016-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15756799 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/756799
Optical proximity correction method and system May 10, 2016 Issued
Array ( [id] => 11233022 [patent_doc_number] => 09460251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-04 [patent_title] => 'Formal verification driven power modeling and design verification' [patent_app_type] => utility [patent_app_number] => 15/139454 [patent_app_country] => US [patent_app_date] => 2016-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5042 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139454 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/139454
Formal verification driven power modeling and design verification Apr 26, 2016 Issued
Array ( [id] => 14458173 [patent_doc_number] => 10325050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => User-defined partitions for logical and physical circuit syntheses [patent_app_type] => utility [patent_app_number] => 15/099299 [patent_app_country] => US [patent_app_date] => 2016-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8717 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15099299 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/099299
User-defined partitions for logical and physical circuit syntheses Apr 13, 2016 Issued
Array ( [id] => 11445446 [patent_doc_number] => 20170046467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'LOGIC STRUCTURE AWARE CIRCUIT ROUTING' [patent_app_type] => utility [patent_app_number] => 15/095390 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4131 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095390
Logic structure aware circuit routing Apr 10, 2016 Issued
Array ( [id] => 14705085 [patent_doc_number] => 10380292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => Systems and methods for finite difference time domain simulation of an electronic design [patent_app_type] => utility [patent_app_number] => 15/094180 [patent_app_country] => US [patent_app_date] => 2016-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15094180 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/094180
Systems and methods for finite difference time domain simulation of an electronic design Apr 7, 2016 Issued
Array ( [id] => 14799055 [patent_doc_number] => 10402532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Methods, systems, and computer program products for implementing an electronic design with electrical analyses with compensation circuit components [patent_app_type] => utility [patent_app_number] => 15/093619 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15093619 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/093619
Methods, systems, and computer program products for implementing an electronic design with electrical analyses with compensation circuit components Apr 6, 2016 Issued
Array ( [id] => 13663685 [patent_doc_number] => 10161999 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-25 [patent_title] => Configurable system and method for debugging a circuit [patent_app_type] => utility [patent_app_number] => 15/091376 [patent_app_country] => US [patent_app_date] => 2016-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15091376 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/091376
Configurable system and method for debugging a circuit Apr 4, 2016 Issued
Array ( [id] => 12350976 [patent_doc_number] => 09952499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Method of fabricating a mask using common bias values in optical proximity correction [patent_app_type] => utility [patent_app_number] => 15/090154 [patent_app_country] => US [patent_app_date] => 2016-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 12054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090154 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/090154
Method of fabricating a mask using common bias values in optical proximity correction Apr 3, 2016 Issued
Array ( [id] => 12243356 [patent_doc_number] => 20180076219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'METHOD AND DEVICE FOR SYNTHESIZING A CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 15/564495 [patent_app_country] => US [patent_app_date] => 2016-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1160 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15564495 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/564495
Method and device for synthesizing a circuit layout Mar 22, 2016 Issued
Array ( [id] => 11359372 [patent_doc_number] => 09536026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Calculating circuit-level leakage using three dimensional technology computer aided design and a reduced number of transistors' [patent_app_type] => utility [patent_app_number] => 15/051334 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/051334
Calculating circuit-level leakage using three dimensional technology computer aided design and a reduced number of transistors Feb 22, 2016 Issued
Array ( [id] => 11345545 [patent_doc_number] => 09529953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Subthreshold standard cell library' [patent_app_type] => utility [patent_app_number] => 15/049762 [patent_app_country] => US [patent_app_date] => 2016-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6180 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15049762 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/049762
Subthreshold standard cell library Feb 21, 2016 Issued
Array ( [id] => 14615273 [patent_doc_number] => 10360339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Method for integrated circuit manufacturing [patent_app_type] => utility [patent_app_number] => 15/043961 [patent_app_country] => US [patent_app_date] => 2016-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15043961 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/043961
Method for integrated circuit manufacturing Feb 14, 2016 Issued
Array ( [id] => 15758357 [patent_doc_number] => 10621294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Semi-local ballistic mobility model [patent_app_type] => utility [patent_app_number] => 15/012734 [patent_app_country] => US [patent_app_date] => 2016-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 15335 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15012734 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/012734
Semi-local ballistic mobility model Jan 31, 2016 Issued
Array ( [id] => 15137477 [patent_doc_number] => 10482210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => System, method, and computer readable medium for walking pads: fast power- supply pad-placement optimization [patent_app_type] => utility [patent_app_number] => 15/000826 [patent_app_country] => US [patent_app_date] => 2016-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12102 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15000826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/000826
System, method, and computer readable medium for walking pads: fast power- supply pad-placement optimization Jan 18, 2016 Issued
Array ( [id] => 14615271 [patent_doc_number] => 10360338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Method for improving capacitance extraction performance by approximating the effect of distant shapes [patent_app_type] => utility [patent_app_number] => 14/996511 [patent_app_country] => US [patent_app_date] => 2016-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5413 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 589 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14996511 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/996511
Method for improving capacitance extraction performance by approximating the effect of distant shapes Jan 14, 2016 Issued
Array ( [id] => 14490101 [patent_doc_number] => 10331841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Methods, systems, and computer program product for implementing virtual prototyping for electronic designs [patent_app_type] => utility [patent_app_number] => 14/997239 [patent_app_country] => US [patent_app_date] => 2016-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14997239 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/997239
Methods, systems, and computer program product for implementing virtual prototyping for electronic designs Jan 14, 2016 Issued
Array ( [id] => 11672703 [patent_doc_number] => 20170161425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'COMPACT MODELING ANALYSIS OF CIRCUIT LAYOUT SHAPE SECTIONS' [patent_app_type] => utility [patent_app_number] => 14/957700 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14957700 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/957700
COMPACT MODELING ANALYSIS OF CIRCUIT LAYOUT SHAPE SECTIONS Dec 2, 2015 Abandoned
Array ( [id] => 13665529 [patent_doc_number] => 10162928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Method of designing a semiconductor device, system for implementing the method and standard cell [patent_app_type] => utility [patent_app_number] => 14/956668 [patent_app_country] => US [patent_app_date] => 2015-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14956668 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/956668
Method of designing a semiconductor device, system for implementing the method and standard cell Dec 1, 2015 Issued
Array ( [id] => 12173145 [patent_doc_number] => 09891281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-13 [patent_title] => 'Method and system for automatically identifying test runs contributing to coverage events of interest in verification test data' [patent_app_type] => utility [patent_app_number] => 14/953463 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5527 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14953463 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/953463
Method and system for automatically identifying test runs contributing to coverage events of interest in verification test data Nov 29, 2015 Issued
Array ( [id] => 11665413 [patent_doc_number] => 20170154132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'POWER-AWARE DYNAMIC ENCODING' [patent_app_type] => utility [patent_app_number] => 14/954391 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11408 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954391 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/954391
Power-aware dynamic encoding Nov 29, 2015 Issued
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