John C. Hong

Array ( [id] => 12229162 [patent_doc_number] => 09916408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Circuit design generator' [patent_app_type] => utility [patent_app_number] => 14/822880 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11445445 [patent_doc_number] => 20170046466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'LOGIC STRUCTURE AWARE CIRCUIT ROUTING' [patent_app_type] => utility [patent_app_number] => 14/821846 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4129 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14821846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12046568 [patent_doc_number] => 09824171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Register file circuit design process' [patent_app_type] => utility [patent_app_number] => 14/820223 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14820223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10764336 [patent_doc_number] => 20160110491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'WRITING DATA VERIFICATION METHOD AND MULTI-CHARGED PARTICLE BEAM WRITING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/819931 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4126 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14819931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11301158 [patent_doc_number] => 09509173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Wireless power transmission and charging system, and impedance control method thereof' [patent_app_type] => utility [patent_app_number] => 14/817806 [patent_app_country] => US [patent_app_date] => 2015-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 15271 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14817806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12167773 [patent_doc_number] => 09886542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Modeling TSV interposer considering depletion capacitance and substrate effects' [patent_app_type] => utility [patent_app_number] => 14/816268 [patent_app_country] => US [patent_app_date] => 2015-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14816268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14253661 [patent_doc_number] => 10277042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Multi-functional charger [patent_app_type] => utility [patent_app_number] => 15/503408 [patent_app_country] => US [patent_app_date] => 2015-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3735 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15503408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12046572 [patent_doc_number] => 09824175 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-21 [patent_title] => 'Method and system of evaluation of validity of a refinement rule for a hardware emulation' [patent_app_type] => utility [patent_app_number] => 14/806745 [patent_app_country] => US [patent_app_date] => 2015-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14806745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703788 [patent_doc_number] => 20160049935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'SYSTEMS, PROCESSES AND COMPUTER-ACCESSIBLE MEDIUM FOR PROVIDING LOGIC ENCRYPTION UTILIZING FAULT ANALYSIS' [patent_app_type] => utility [patent_app_number] => 14/797841 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6120 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14797841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10432412 [patent_doc_number] => 20150317424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'SYSTEM AND METHOD FOR OPTIMIZATION OF AN IMAGED PATTERN OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/798331 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11924818 [patent_doc_number] => 09792402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-17 [patent_title] => 'Method and system for debugging a system on chip under test' [patent_app_type] => utility [patent_app_number] => 14/755071 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4938 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14755071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11366263 [patent_doc_number] => 20170004244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'LOOK-AHEAD TIMING PREDICTION FOR MULTI-INSTANCE MODULE (MIM) ENGINEERING CHANGE ORDER (ECO)' [patent_app_type] => utility [patent_app_number] => 14/788051 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4411 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11366252 [patent_doc_number] => 20170004233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'METHOD OF SIMULTANEOUS LITHOGRAPHY AND ETCH CORRECTION FLOW' [patent_app_type] => utility [patent_app_number] => 14/788296 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8283 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10658653 [patent_doc_number] => 20160004797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'CIRCUIT DESIGNING SUPPORT APPARATUS AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/755977 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4869 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14755977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11990745 [patent_doc_number] => 20170294900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'Method for the automated manufacture of an electronic circuit suitable for detecting or masking faults by temporal redundancy, and associated computer program and electronic circuit' [patent_app_type] => utility [patent_app_number] => 15/321568 [patent_app_country] => US [patent_app_date] => 2015-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14461 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15321568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12951331 [patent_doc_number] => 09836571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Applying random nets credit in an efficient static timing analysis [patent_app_type] => utility [patent_app_number] => 14/747611 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6581 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14747611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10764042 [patent_doc_number] => 20160110197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'PROCESSOR STRESSMARKS GENERATION' [patent_app_type] => utility [patent_app_number] => 14/743104 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5727 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13706015 [patent_doc_number] => 20170363962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => LITHOGRAPHY SYSTEM, SIMULATION APPARATUS, AND PATTERN FORMING METHOD [patent_app_type] => utility [patent_app_number] => 15/315073 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -47 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15315073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10377641 [patent_doc_number] => 20150262648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/727537 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17933 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10733644 [patent_doc_number] => 20160079795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'MODULAR POWER GENERATION AND ENERGY STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 14/720402 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14720402 [rel_patent_id] =>[rel_patent_doc_number] =>)