Search

John C. Hong

Examiner (ID: 1779, Phone: (571)272-4529 , Office: P/3726 )

Most Active Art Unit
3726
Art Unit(s)
3726
Total Applications
2343
Issued Applications
1904
Pending Applications
53
Abandoned Applications
396

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13069507 [patent_doc_number] => 10055533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Visualization of analysis process parameters for layout-based checks [patent_app_type] => utility [patent_app_number] => 14/716775 [patent_app_country] => US [patent_app_date] => 2015-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7091 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14716775 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/716775
Visualization of analysis process parameters for layout-based checks May 18, 2015 Issued
Array ( [id] => 11272838 [patent_doc_number] => 20160335385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'Method of Lithography Process with Inserting Scattering Bars' [patent_app_type] => utility [patent_app_number] => 14/713360 [patent_app_country] => US [patent_app_date] => 2015-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14713360 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/713360
Method of lithography process with inserting scattering bars May 14, 2015 Issued
Array ( [id] => 11272837 [patent_doc_number] => 20160335383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'AREA-EFFICIENT MEMORY MAPPING TECHNIQUES FOR PROGRAMMABLE LOGIC DEVICES' [patent_app_type] => utility [patent_app_number] => 14/713991 [patent_app_country] => US [patent_app_date] => 2015-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14713991 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/713991
Area-efficient memory mapping techniques for programmable logic devices May 14, 2015 Issued
Array ( [id] => 12229166 [patent_doc_number] => 09916411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Negative plane usage with a virtual hierarchical layer' [patent_app_type] => utility [patent_app_number] => 14/713488 [patent_app_country] => US [patent_app_date] => 2015-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14190 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14713488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/713488
Negative plane usage with a virtual hierarchical layer May 14, 2015 Issued
Array ( [id] => 10409031 [patent_doc_number] => 20150294039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'Graphical Design Verification Environment Generator' [patent_app_type] => utility [patent_app_number] => 14/678138 [patent_app_country] => US [patent_app_date] => 2015-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11199 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14678138 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/678138
Graphical design verification environment generator Apr 2, 2015 Issued
Array ( [id] => 10409029 [patent_doc_number] => 20150294038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'Graphical Design Verification Environment Generator' [patent_app_type] => utility [patent_app_number] => 14/678067 [patent_app_country] => US [patent_app_date] => 2015-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11199 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14678067 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/678067
Graphical design verification environment generator Apr 2, 2015 Issued
Array ( [id] => 12201690 [patent_doc_number] => 09904756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs' [patent_app_type] => utility [patent_app_number] => 14/675516 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 14683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675516
Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs Mar 30, 2015 Issued
Array ( [id] => 11614721 [patent_doc_number] => 09652578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Layout design methods and layout design systems for performing the layout design methods' [patent_app_type] => utility [patent_app_number] => 14/674416 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14674416 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/674416
Layout design methods and layout design systems for performing the layout design methods Mar 30, 2015 Issued
Array ( [id] => 13651885 [patent_doc_number] => 09852258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-26 [patent_title] => Method and system for implementing a requirements driven closed loop verification cockpit for analog circuits [patent_app_type] => utility [patent_app_number] => 14/675551 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675551 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675551
Method and system for implementing a requirements driven closed loop verification cockpit for analog circuits Mar 30, 2015 Issued
Array ( [id] => 11910380 [patent_doc_number] => 09779193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Methods, systems, and computer program product for implementing electronic design layouts with symbolic representations' [patent_app_type] => utility [patent_app_number] => 14/675665 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 10910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675665 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675665
Methods, systems, and computer program product for implementing electronic design layouts with symbolic representations Mar 30, 2015 Issued
Array ( [id] => 10550556 [patent_doc_number] => 09275182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Placing transistors in proximity to through-silicon vias' [patent_app_type] => utility [patent_app_number] => 14/674462 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 11637 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14674462 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/674462
Placing transistors in proximity to through-silicon vias Mar 30, 2015 Issued
Array ( [id] => 11637163 [patent_doc_number] => 09659138 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-23 [patent_title] => 'Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques' [patent_app_type] => utility [patent_app_number] => 14/675609 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 14232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675609 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675609
Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques Mar 30, 2015 Issued
Array ( [id] => 14669907 [patent_doc_number] => 10372855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Scan cell selection for partial scan designs [patent_app_type] => utility [patent_app_number] => 14/633999 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6179 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633999 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633999
Scan cell selection for partial scan designs Feb 26, 2015 Issued
Array ( [id] => 10363515 [patent_doc_number] => 20150248520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'Method and Apparatus for Physical-Aware Hold Violation Fixing' [patent_app_type] => utility [patent_app_number] => 14/633477 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9376 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633477 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633477
Method and apparatus for physical-aware hold violation fixing Feb 26, 2015 Issued
Array ( [id] => 11509453 [patent_doc_number] => 09600613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-21 [patent_title] => 'Block-level code coverage in simulation of circuit designs' [patent_app_type] => utility [patent_app_number] => 14/633417 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633417
Block-level code coverage in simulation of circuit designs Feb 26, 2015 Issued
Array ( [id] => 10417121 [patent_doc_number] => 20150302131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'INFORMATION PROCESSING APPARATUS AND BACK ANNOTATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/632156 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5430 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632156 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/632156
INFORMATION PROCESSING APPARATUS AND BACK ANNOTATION METHOD Feb 25, 2015 Abandoned
Array ( [id] => 11903651 [patent_doc_number] => 09773085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'System design management' [patent_app_type] => utility [patent_app_number] => 14/610948 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9058 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14610948 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/610948
System design management Jan 29, 2015 Issued
Array ( [id] => 11846718 [patent_doc_number] => 09734274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'System design management' [patent_app_type] => utility [patent_app_number] => 14/610954 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14610954 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/610954
System design management Jan 29, 2015 Issued
Array ( [id] => 11193572 [patent_doc_number] => 09424387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Methods for cell phasing and placement in dynamic array architecture and implementation of the same' [patent_app_type] => utility [patent_app_number] => 14/605946 [patent_app_country] => US [patent_app_date] => 2015-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 12364 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14605946 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/605946
Methods for cell phasing and placement in dynamic array architecture and implementation of the same Jan 25, 2015 Issued
Array ( [id] => 10250150 [patent_doc_number] => 20150135146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'THREE-DIMENSIONAL MASK MODEL FOR PHOTOLITHOGRAPHY SIMULATION' [patent_app_type] => utility [patent_app_number] => 14/600337 [patent_app_country] => US [patent_app_date] => 2015-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7263 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14600337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/600337
Three-dimensional mask model for photolithography simulation Jan 19, 2015 Issued
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